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The Booth multiplier is a very fast multiplier with minimum latencies. In this paper, a typical architecture of Booth Encoder and Wallace tree is presented, In which we have implemented pipelining at the intermediate nodes of the modules present in it. The architecture comprises of four modules, they are as follows, One's Complement generator, Booth Encoder, Partial product generator and Wallace tree...
Embedded and ubiquitous sensors are driving industry to look for low power solutions for complex DSP algorithms; system engineers are also looking for upgradable capability to higher throughput and algorithm enhancements. Many-core, parallel architectures seem to be a solution to meet these interests at the same time. However it introduces a challenging problem: the programmability of a many-core...
This paper aims the hardware co-simulation of parameterized Walsh code with classical counter architecture using MATLAB SIMULINK based Xilinx System Generator software tools. This is an implementation of the theory which replaces a general Sine and cosine function by set of orthogonal functions such as Rademacher functions and Walsh functions. We investigate 64-orthogonal set for 3G standard such...
The low latency and high throughput requirements of high-frequency trading has resulted in increasing adoption of dedicated hardware for processing financial feeds. Development of hardware platforms, however, is plagued with slow design/verification cycles compared to their software counterparts. In this work, we present FINPAGE, a FINancial PArser GEnerator, to automatically generate hardware structures...
Arithmetic circuits are some of the most common circuits, yet building generators for these circuits is usually both ad-hoc and error-prone. Often, generator designers do not directly use Register Transfer Languages, but instead use scripting languages (e.g., Perl) to generate RTL and overcome the limited expressivity of typical RTL languages. We present a new approach to generator construction, where...
In decentralized supervisory control, several local control agents (supervisors) cooperate to achieve a common goal, expressed by a safety specification and/or by nonblockingness. It is well-known that coobservability is the key condition to achieve the specification as the resulting language of the controlled system. One of the most important problems is to compute a coobservable sublanguage of the...
Signal generators, also known as function generators, they are electronic devices that generate repeating or non-repeating electronic signals in either the analog or digital form. They are generally used in designing, testing, troubleshooting, and repairing electronic or electro acoustic devices, though they often have artistic uses as well. Many features added to function generators have complicated...
The RDF framework is the underpinning element of Semantic Web stack, its widespread adoption requires efficient tools to store and query RDF data. A number of efficient local RDF stores already exist, while distributed indexing and distributed query processing are only starting to develop, furthermore dynamically growing and fail-safe solutions are not yet available. To remedy this situation, we propose...
Power consumption is a critical issue in functional unit design. Focusing on the condition of the positive narrowwidth operands, this paper presents a low-power multiplier. Compared with the baseline multiplier, an additional width detector is employed in front of the operand register in the proposed multiplier. With the width information supplied by the width detector, computation modules in the...
Long Term Evolution (LTE) supports peak data rates in excess of 300 Mb/s. A good approach to achieve such rates is by parallelizing the required processing in turbo decoders. An interleaver is an important part of a turbo decoder. LTE uses the Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for parallel decoding. In this paper, we propose an efficient architecture for the...
The wide spread of application specific processors like network or communication processors generated the need of optimizing retargetable software development tools such as compiler, linker, debugger, assembler and simulator. In order to quickly develop these tools for multiple design points under consideration, it is highly desirable to have them synthesized from formal processor descriptions written...
This paper presents a cache-centric, hash-based architecture within a application specific integrated circuit (ASIC) implementation for IPv6 routing lookup system. In ASIC, the binary content addressable memory (BCAM) as cache memory has a hit ratio of up to 80% with a FIFO replacement algorithm. A hash function is used to reduce lookup time for the routing table and ternary content addressable memory...
Raptor codes can provide good error correction capability and efficient encoding and decoding rates. Its fountain code property is effective in avoiding packet retransmission for both unicast and multicast service delivery. Hence, there are many wireless and broadband applications adopting it such as mobile multimedia broadcasting and broadband IPTV systems. In this paper, we present an efficient...
Universal asynchronous receiver transmitter, abbreviated DART is a integrated circuit used for serial communications over a computer or peripheral device serial port. DARTs are now commonly included in microcontrollers. The universal designation indicates that the data format and transmission speeds are configurable and that the actual electric signaling levels and methods (such as differential signaling...
Nowadays, computer vision algorithms have countless application domains. On the one hand, these algorithms are typically computationally demanding, on the other hand, they are often used in embedded systems, which have stringent constraints on, e. g., size or power. In this work, we present the benefits of mapping compute-intensive imaging algorithms on programmable massively parallel processor arrays...
Modern processor design tools integrate in their workflows generators for instruction set simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful for design evaluation and software development, they suffer from poor performance. We present an ultra-fast Jit-compiled Iss generated from an ArchC description. We also introduce a novel partial evaluation optimisation,...
The usage of smart phones is increasing rapidly over the last few years. Due to their mobility and good connectivity, smartphones are increasing thrice as compared to PCs. However they are still constrained by limited processing power, memory and Battery. Thus, the applications cannot be made very rich. In this paper we propose a framework for making the applications of these smartphones intelligent...
Cyclic Redundancy Check (CRC) is a well known error detection scheme used to detect corruption of digital content in digital networks and storage devices. In this paper, we present a study of different approaches of designing highly adaptable co-processors for CRC on an FPGA which are used in many network and server applications. The results of our research are two new architectures: adaptable and...
This paper presents a very lean DSP Extension Architecture (iDEA) soft processor for Field Programmable Gate Arrays (FPGAs). iDEA has been built to be as lightweight as possible, utilising the run-time flexibility of the DSP48E1 primitive in Xilinx FPGAs to serve as many processor functions as possible. We show how the primitive's flexibility can be leveraged within a general-purpose processor, what...
We present a hardware architecture for efficient implementation of a Gaussian random number generator (GRNG), using the Monty Python method. To maximize the performance/complexity efficiency, an efficient word-length optimization model is proposed to find out both the optimal integer and fractional word-lengths for signals. Experimental results show that our optimized Fixed-Point design achieves a...
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