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A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC. This paper proposes constant-slope charging as a method to realize a DTC with intrinsically better integral non-linearity (INL) compared to the popular variable-slope method. The proposed DTC chip realized in 65 nm CMOS consists...
The fast performance of a carry-lookahead adder (CLA) comes from the ability to input a carry signal into each full adder block that depends on all preceding adder blocks. While the translation of this carry signal logic into CMOS transistors has a unique solution, this paper demonstrates that there are four different ways to connect the PMOS and NMOS transistors to Vdd, ground, and the output. Each...
A high resolution Vernier Ring Time-to-digital Converter is presented in this paper. Body bias is applied to its delay cells to obtain a finer delay difference between two delay chains. The delay cells and arbiters are implemented in a ring structure, thus allowing a large input time interval to be measured. The digital circuit nature of this converter is also attractive for low power and small area...
Time-Based Analog-to-Digital Converter (ADC), at scaled CMOS technology, plays a major role in designing Software Defined Radio (SDR) receivers as it manifests higher speed and lower power than conventional ADCs. Time-Based ADC includes a Voltage-to-Time converter (VTC) which converts the input voltage into a pulse delay, and a Time-to-Digital Converter which converts the pulse delay into a digital...
In this paper a four-stage self-biased voltage-controlled oscillator (VCO) is presented. The proposed ring-oscillator circuit employs a combination of dynamic-threshold-MOS (DT-MOS) and bulk-driven transistors to design low-voltage low-power VCO with high oscillation frequency. By using an auxiliary body-driven latch, the VCO achieves a wide operating frequency range from 0.88 to 1.36 GHz (more than...
Ultra wideband radar implementations for millimeter-/microwave operation are emerging in CMOS requiring high bandwidth. A distributed amplifier (DA) topology for use as low-noise amplifier (LNA) in nanometer CMOS, is explored in this paper. Important modifications like direct termination is beneficial both in area and gain linearity. A 5-stage amplifier provides a −3dB bandwidth of 36.5GHz and a S...
This paper presents a 12-bit hybrid successive approximation register (SAR) analog-to-digital converter (ADC) composed of common-mode based switching procedure and time-to-digital converter (TDC). For high-resolution requirement, several issues including the signal-dependent coupling in bootstrapped sample-and-hold circuit and parasitic loading effect of voltage-to-time converter are addressed by...
This paper investigates the impact of voltage scaling on the energy and the performance of STT-RAM bitcells during write operation. Analytical models of energy scaling and performance degradation are derived to gain an insight into the energy-performance tradeoff at low voltages. Minimum-energy operation is explored through optimization of the supply voltage, with energy savings in the order of 20%...
The key parameters for the performance measure of any VLSI design are logic delay, power consumption and chip area. This paper describes the VLSI design of a 16 Bit ALU and design is optimized in terms of Speed, Power Consumption and Chip Area. Different logic families are used in the design for various logic modules. The choice of logic families for each module is determined by considering speed...
This paper describes DD1, an asynchronous radiation-hard 8-bit AVR (R) microcontroller (MCU) implemented in TSMC 40LP, a low-power bulk 40nm CMOS process. Designed for extreme reliability, DD1 uses quasi-delay-insensitive (QDI) asynchronous logic and contains full-custom radiation-hard memories and logic cells. The chip was found fully functional on first silicon over a range of operating voltages...
In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentage of the total power dissipation and rises exponentially according to the International Technology Roadmap for Semiconductor (ITRS). Here a wide-ranging survey and analysis has been done for leakage reduction based on active as well as idle mode of operation. This paper proposes a novel approach, based...
Spin torque nano oscillators (STNOs) are one of the most promising devices for generating high frequency radio waves because of high efficient operation with wide frequency tenability and long durability [1]. Since the output-power of a single STNO is still limited due to low driving voltage, cooperation of many STNOs is required for increasing the total power. For the purpose, several synchronization...
For many processing operation addition forms the basis, that is from counting to multiplication to filtering. As a result adder circuit are important therefore we have proposed design of quaternary adders such as quaternary ripple carry adder, quaternary carry look-ahead adder, quaternary carry select adder. The various quaternary adders shows power consumption of 64% less as compared to binary circuits...
In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to...
Memristive devices enable non-volatile data storage and in-memory computing capabilities. By using stateful logic approaches, hybrid CMOS nano-crossbar arrays offer additional functionalities such as arithmetic operations. To enable storage and computing on large-scale arrays, parasitic current paths within the array must be avoided. Therefore, for example, a complementary resistive switch (1CRS)...
An all-digital delay-locked loop (ADDLL) is proposed for wide range, fast lock, low jitter and high process-voltage-temperature (PVT) tolerance. The proposed phase tracking generator (PTG) produces two tracking rising and falling phases in only 2 cycles for fast lock and wide-range. The digital phase interpolator (DPI) and the control block are adopted to calibrate the phase offsets and random jitters...
An integrated circuit has been developed for a basic nonlinear negative feedback current driver which isolates the poles required for stability from the high frequency characteristics of the output transconductor. It provides a 1 MHz, 1 mAp-p current with a phase delay of 16° into a1kΩ load. While it can be designed as a stand-alone circuit its main use is for application in a proposed circuit using...
This paper presents the design and performance analysis of a ring oscillator using CMOS 90nm technology. A ring oscillator contains odd number of cascaded inverter in which output is oscillating between high and low level. Inverter with minimum delay is best choice for frequency generation. Delay of inverter can reduce by adding secondary inputs and switching these earlier than the primary inputs...
In this paper, we describe two single input threshold gate (TLG) designs, which are functionally equivalent to differential flipflops. We present a detailed comparison of TLGs with two well established D-flipflop designs. The comparisons are done in both 65nm and 28nm commercial processes. We compare total delay, which is defined as the sum of setup delay and clock to output delay. We also show a...
This article explores the use of threshold logic for reducing the power, delay, and/or area of digital logic circuits. We first describe the architecture of a differential threshold logic gate (TLG) using conventional MOSFETs. A TLG of a given number of inputs can be configured to realize a set of threshold functions by simply connecting the appropriate signals to its inputs. One characteristic of...
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