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Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
SiC semiconductor devices are becoming more common in high power applications. This is largely due to higher blocking voltages and faster switching speeds. The development of SiC devices, specifically thyristors and GTOs, is still an evolving process [1]. There is not yet a single device capable of handling the magnitude of current typically seen in transmission and distribution systems and as a result...
We have successfully demonstrated top-gate a-Si TFT with self-aligned nickel silicide source/drsain (S/D). We have shown, by examining contact resistance, the dominant electron injection mechanism is tunneling from silicide S/D to the channel. Further, we show that the contact resistance has no influence on device threshold and little effect on effective mobility down to L=5 mum.
The Epitaxy Wrap-through (EpiWT) cell concept is introduced. It combines the benefits of rear-side contacting with the low-cost potential of epitaxial crystalline silicon thin-film technology. Its advantage over the standard EWT cell upon which it is based is the simplified rear structuring due to the inactive substrate. This paper focuses on the development of the key process: the epitaxial deposition...
This paper presents a wideband circuit model of silicon-based interconnects for predicting their metallic and silicon substrate losses at higher frequencies. The skin and proximity effects in the structure are characterized using the partial element equivalent circuit (PEEC) method, and the parasitic parameters in silicon substrate are captured according to some analytical equations. Good agreements...
In this paper, we show the electrical characteristics of TSV (through silicon via) depending on structural parameters such as TSV pitch, TSV height, TSV size and thickness of SiO2 for DC leakage blocking between TSV and silicon substrate, and material parameter of silicon substrate such as silicon resistivity in case of single silicon substrate. And we also show X-talk characteristics of two TSVs...
The polycrystalline samples of BaSi2, SrSi2, and LaSi were prepared by spark plasma sintering (SPS). The electrical resistivity (rho) and Seebeck coefficient (S) were measured above room temperature. The S of BaSi2 was negative and the absolute values were rather high (-669 muVK-1 at 337 K). The S of SrSi2 was positive and the absolute values were lower (118 muVK-1 at 332 K) than those of BaSi2. For...
The present work aims at studying the cooling performance of a thermoelectric device that integrated with integrated heat spreader (IHS) on a flip-chip plastic ball grid array (FC-PBGA) package. The new thermoelectric device herein is fabricated on the metal substrates by flip-chip assembly process. Thermal performance of the new package was comprehensive studied. The thermal resistances of IHS with/without...
In this study, we fabricated in-plane thermoelectric micro-generators (4 mm times 4 mm) based on bismuth telluride thin films by using flash evaporation method. The thermoelectric properties of as-grown thin films are lower than those of bulk materials. Therefore the as-grown thin films were annealed in hydrogen at atmospheric pressure for 1 hour in a temperature range of 200 degC. to 400degC. By...
It is shown that bonded SOI structures can be qualified for device fabrication through a series of eletrical measurements without fabrication of special test strucutres. The electrical methods include MOSCV, MOSIV, point contact MOS transistor (PCMOST) measurements, and spreading resistance profiling. It was found that buried oxide charge, contamination, and dopant segregation significantly impact...
A permeable base transistor (PBT) has been fabricated by local implantation of 59Co into Si(100) with subsequent rapid thermal annealing and epitaxial growth of silicon by LPVPE. Transmission electron microscopy shows abrupt interfaces between the buried CoSi2 and the adjacent silicon. Rutherford backscattering and channeling experiments with a minimum yield of 5.3% for the Co signal as well as a...
Shallow p+-n junctions have been achieved employing substrate prcamorphization with gallium implantation prior to high dose boron or BF2 implantation. The resulting p+-n junctions are investigated and compared with junctions obtained with conventional techniques. The impact of different amorphization procedures on boron diffusivity is explained by analytical models.
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