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Ever increasing stringent reliability requirements in semiconductor package demands a mold compound with a property of resisting package crack under stress condition of High Temperature Storage (HTS) at 175°C, compatible with package assembly material such as copper interconnect, High Humidity High Temperature Gate Stress (H3TGS) as well as meeting second level reliability test in Thermal Cycle on...
Conventional method to define the useful tool life is by punching the actual molded units in trim and form (TNF) machine. Throughout the punch intervals, the punched leadframes were sent for inspection for any side burr observed at the leads. This process might take several days or weeks in order to reach the end of punch tool lifespan. It is quite a manual and time consuming task, if it involves...
Through mold interconnects (TMI) is a key enabler for fan-out wafer level packaging (FOWLP) for 3D integration. Three different types of TMI have been developed for both mold-first and RDL-first fabrication flow. The three types of TMI consist of laser drilled vias, vertical wire-bonds and Cu pillars interconnect. The process flow and fabrication results of each TMI will be presented in this paper.
From the aspect of package design, when ASIC and FPGA are compared, the considerations are vastly different. FPGA design cycle is short and crucial time to market to supports multiple application domains and the package matrix needs to have vertical and horizontal migration. Hence, FPGA package designs need to have scalable design concept to drive short design cycle time for comparatively fast market...
This paper describes ultra-fine pitch 3D integration development using wafer level Cu/insulator hybrid bonding approach on 300mm substrate. Via-middle process with TSV dimension of 5×50μm is utilized to demonstrate and characterize vertical interconnects formed via face-to-face wafer-to-wafer (W2W) bonding. Key process steps are introduced with specific requirements and challenges. A non-SiO2 insulator...
Bare die flip chip products have a high risk of die cracking as shown in Figure 1, during product electrical test or temperature cycling. The stresses experienced by the die during these events are understood. But the die strength impact after product laser marking on the die backside is not well understood. This area has a lot of room for improvement. Often, a lid is added to a flip chip package...
In this study, low temperature TEOS oxides were deposited by plasma enhanced chemical vapor deposition (PECVD) at 100°C, 150°C and 180°C respectively. After deposition, physical characterization was carried out by FTIR for chemical bonding condition, AFM for surface roughness, Auger electron spectroscopy for chemical composition, ellipsometer for refractive index, and DHF for wet etching rate measurement...
The Ball grid array (BGA) product fixed on the PCB under Highly Accelerated Stress Test (HAST) reliability test and its relevant corrosion phenomenon are reported. In this article, BGA performed HAST with the socket which individually interconnect between BGA device and PCB test board is subjected to provide moisture path and transfer the applied bias to the PCB. Oxidation and corrosion are found...
Nowadays, many electronic products are exposed to harsh climatic conditions, and hence the protection of these devices is a crucial factor in design of systems. Therefore, the modelling tools have become very useful in the electronics design which supports the search of optimal electronics design and humidity control solutions. While high fidelity CFD codes are too time consuming due to computational...
Mission profiles for specific automotive applications are becoming more and more demanding from the reliability point of view. Translating this challenging requirements into reliability targets, it means performing trials for longer duration, or using more accelerated conditions (increasing temperature or voltage, etc…). This study is focused on the understanding of the failure mechanism and the characterization...
As demand for smaller and faster electronic products increases rapidly, 3D packaging with higher electrical performance and density are desirable [1]. Flip chip interconnection technologies using copper pillars have been widely used in many microelectronic applications for high performance systems as well as consumer electronics in recent years [2]. The technology offers improved electrical and thermal...
According as high density packaging options such as multi-die staking or package stacking technologies are developed, the major mold process related quality concerns such as severe air void entrapment under the die. The accurate analysis of venting is important for realistic prediction of voids that may occur during chip encapsulation. This study reports a perspective investigation of computational...
Investigations of alternative Cu-based alloys were carried out as an opportunity for improvement on the quality, reliability and cost reduction. CuFeP and CuCr were successfully evaluated as an alternative leadframe alloys to the existing CuZr alloy on a wheel-speed magnetic sensor package through thermo-mechanical simulation, assembly and test performance, and reliability tests performance. Material...
Multi-Project Wafer (MPW) is designed for cost saving and fast prototype but conventional Blade Dicing process is time consuming and high risk to cause die loss because repetitive Blade Dicing process. Stealth Dicing is an alternative solution of Blade Dicing, patterned by Hamamatsu Photonics, which has potential for MPW dicing solution. This paper presents first successful MPW dicing by Stealth Dicing...
Cu-Ni-Pd bonding pads are used extensively in high current wirebonded devices. However in certain cases, there is a susceptibility to discoloration caused by copper re-deposition on the palladium surface. To prevent this mechanism, the best solution is to remove the Cu ions or the electrolyte. Initial evaluations were done using a surfactant with a chelating agent to prevent Cu ions from re-depositing...
In this paper, novel microwave double-side calibration and measurement technology is presented. The thru kit which is the key element in the SOLT (Short, Open, Load, Thru) calibration method will be modified into the novel double-side thru calibration kit. And through novel double-side calibration kit, that can accomplishment the GSSG to GSSG four port calibration. For this purpose, there are two...
Fan Out-Wafer Level Packaging (FO-WLP) has been recognized as the main electronic packaging and integration technology. It is cost effective and has good electrical performance as compared to the Silicon Interposer. Currently, there are many different versions of this FO-WLP technology being developed with the objective to increase the routing density. In order to design integrated circuit or package...
High lead solder has a long history of use in the semiconductor industry as a die attach and interconnect material within high-current-density discrete power packages. The main reason high Pb solder is still an ideal material and cannot be replaceable until today because of its low resistance, high thermal conductivity for improved electrical performance, ductility to accommodate thermal expansion...
Through-silicon via (TSV) is a key enabler for future 3-D integrated circuits. Due to MOS (Metal-Oxide-Semiconductor) effect, the coupling capacitor between TSVs is actually a varactor under different signal/power voltages. This paper offers a discussion on the stabilization and utilization of the TSV varactor for different systems. For digital systems, it is important to ensure that TSV capacitance...
Wafer bumping and flip chip bonding are gaining momentum in the semiconductor packaging arena with the increase in pin count, smaller pad pitch and electrical performance. The cost of wafer bumping and flip chip bonding always hinder the growth for adoption. This paper introduces a patented wafer bumping process known as Double Resist Imaging Process (DRIP) which enables electrolytic wafer bumping...
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