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Alloyed silver (Ag) based bonding wires reveal bondability comparable to Au wires. The present paper discusses on: • Axi-symmetrical free air ball (FAB) formation of Ag remains a challenge due to lower surface tension property of molten Ag compared to molten gold/copper (Au/Cu) • Soft Ag FAB/wire reveals a wide workable ball/stitch bond process window similar to Au FAB/wire • Concentric Ag ball bond...
The effects of temperature cycling from −40°C to 250°C on the active metal brazing (AMB) substrates were investigated using silicon nitride ceramics or aluminum nitride ceramics with different fracture toughness and strength. Visual inspection of the substrates after 1000 cycles hardly detected failure in the Si3N4-AMB substrates with the high fracture toughness of 8.0 MPa·m1/2. By contrast, the Si...
System-in-Package (SiP) is becoming more and more important in integrating functionality while reducing final product form factors and cost. This is particularly true for mobile applications where continued effort to achieve ever smaller products is continuously pushing development of new materials, components and assembly technologies. An optimization study of a SiP design based on a functional product...
Conventional through silicon via (TSV) Cu electroplating produces excessive Cu overburden, which is deposited on wafer surface. Cu overburden can cause wafer warpage and has to be removed by chemical mechanical polishing (CMP) for following process. We developed new approach to reduce Cu overburden by combining TSV Cu electroplating and chemical seed layer etching. Process parameters for 1st TSV Cu...
In this paper, a novel HT (high thermal) 3D package structure with 5-side heatsinks is designed to enhance, if not resolve, the heat dissipation capability constraints as encountered by current conventional stacked dies 3D package. This new package not only improves on current 3D package thermal constraints, but also can be easily implemented with low cost 2 layer flexible substrate design. So such...
This paper describes the design of a high efficiency energy harvesting circuit combined with antenna. The circuit is composed of a series resonance circuit and boosting rectifier circuit for converting radio frequency power into a DC boosted voltage. For further efficiency improvement, input impedance of antenna is optimized. The simulated output DC voltage is 9.0V for an input of 100mV at 900MHz.
Ultrasonic is one important factor of ultrasonic wire bonding process, which is widely used in semiconductor packaging industry. Control effect of ultrasonic power determines the quality and speed of wire bonding. Based on analysis of ultrasonic frequency characteristics and current response, this paper proposes a closed-loop control method of automatic frequency tracking and output current control,...
Fan-Out Wafer Level Packaging (FOWLP) was proposed and introduced due its advantages in cost reduction [1] and enhanced packaging capabilities. However, there are still many challenges relating to yield loss and manufacturability [1],[2],[3]. In addition, there is also an increasing demand for the Cu Redistribution Layer (RDL) to achieve finer resolution with higher thickness. In this evaluation,...
Low density micro-bumps were required for assembly of different technologies connection within 3D and 2.5D packaging. 6μm and 8um bump heights after reflow are required for 15μm and 25μm (Cu/SnAg) diameter micro-bump, respectively. At same time, the pattern density of 15um and 25μm diameter micro-bump are 0.045% and 0.127%. This paper reported the process challenges, evaluation and development. The...
This paper describes a new evaluation method of resin delamination strength at the adhesive interface. Power module consists of different materials. Difference of thermal expansion between the dissimilar materials causes the delamination at their interface. The new pudding-cup test method has been used to evaluate the delamination stress, where singular stress or stress intensity factors are used...
In the 3D integration stages, the structure of the TSV is changed with the development of the procedure. The 3D though silicon via (TSV) integration models with the new updated structure depended on the integration processes (fabricating redistribution layer (RDL), reflowing solders and filling underfill) were analytically studied in this work. The equivalent stress, von Mises stress, was used to...
This work mainly focused on the heat dissipation of the 3D integrated circulates (ICs). In order to satisfy the urgent heat dissipation needs, the optimal design of heat sink and optimized path for transmitting heat is one of the most promising and effective ways. Two methods have been proposed for solving the heat dissipation issues. First one was the optimized microchannel with pin fin integrated...
Wire bonding as well as wafer probing can lead to oxide layer cracking in Backend of Line (BEOL) Bond Pad Stacks. This, along with metal migration into formed cracks, may lead to electrical failures. Mechanical loading conditions comparable to those during the wafer test and the wire bonding process can be achieved using a nanoindenter. This work addresses the finite element (FE) simulation of an...
Ball attach on ultra-thin 200 mm TAIKO wafers is considered a challenge but it can be mastered. The TAIKO wafer grinding concept is based on the thinning of an inner area of a silicon wafer leaving an outer ring as stiffening frame for wafer handling without an additional carrier [1]. The process development methodology for a near industrial TAIKO wafer balling pilot line is described. A phased process...
Recently, sintering joint using Ag-nano has been attracting attention as a new joint method to replace the solder. However, the joint layer would contain a lot of voids after sintering processes. Since the voids affect mechanical property, the proper sintering conditions have to be selected in order to reduce these voids. In this research, the authors focus on the effect of pressure conditions at...
When dealing with production of Flip Chip Packages in semiconductor packaging the angle between the die and package substrate is critical for maintaining product yield and reliability. Current outgoing quality checks for die tilt can be time consuming to measure heights via point to point measurement techniques. Existing die tilt measurement approaches can also have reproducibility issues from user...
The paper reviews structuring methods of adhesive layers which can be subsequently used for thermo-compression type wafer to wafer bonding processes. With respect to limitations of the state-of-the-art adhesive structuring approaches laser direct patterning of polymer resins is introduced. The process features a 248 nm excimer laser stepper with mask based pattern projection and high speed XY-moving...
Pure Gallium metal is a good adhesive agent which can be used to paste small coupons on full wafer for metal growth in high temperature PVD chamber as Ga has low vapor pressure in high temperature. However, when the process chamber exceeds a certain critical temperature, Gallium at the back of the coupon can contaminate front metal surface in process chamber to form a Ga rich metal surface layer....
The reliability of electronic substrates at high temperature is a significant issue for high-power semiconductor modules. To improve the reliability, it is essential to understand and reduce thermal-cycling-induced surface roughening of metal layers on the substrates. We observed the surfaces and cross sections of nickel plating layers on copper-metallized silicon nitride substrates by active metal...
System-in-Package (SiP) is becoming more and more important in integrating functionality while reducing final product form factors and cost. This is particularly true for mobile applications where continued effort to achieve ever thinning products is continuously pushing development of new materials, components and assembly technologies. Typically, SiP's with LGA pads need to be attached with solder...
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