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In this work, the design of a prototype chip for signal integrity characterization in 130 nm CMOS technology is discussed. Measurement results for several interconnect configurations are presented. The goal is to accurately capture and characterize the transmission line properties of deep-submicron interconnects in order to generate guidelines for multi-GHz clock rate designs.
A customized reconfigurable interconnection network (CRIN) refers to a minimal switching network, yielding routing solutions for any element in a pre-given set of routing requirements. The CRIN design problem looks for the best performance and resource-flexibility trade-off between two extreme design contexts ASIC and FPGA. In this paper we give the modeling of this problem for both directed and undirected...
Due to advanced process technologies the decreasing distance between wires has led to significant bus interferences that introduce crosstalk delay and noise. We first propose two encoding schemes, namely DUCE and GASIE, that can reduce crosstalk delay and noise on the bus lines. The DUCE scheme is a temporal encoding so it needs no additional bits to implement. It can be easily used in existing systems...
Networks on chips (NoCs) provide a mechanism for handling complex communications in the next generation of integrated circuits. At the same time, lower yield in nano-technology, makes self repair communication channels a necessity in design of digital systems. This paper proposes a reliable NoC architecture based on specific application mapped onto an NoC. This architecture is capable of recovering...
In this paper, we present a new technique to improve the reliability of H-tree SRAM memories. This technique deals with the SRAM power-bus monitoring by using built-in current sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the inversion of the state of...
Nowadays, one chip can integrates up to 4 billion transistors. Therefore, how to deal with the connection between its different components efficiently becomes critical. Network on chip is a promising technology to handle with the connection problems. In this paper, a NoC traffic model is extracted based on the longtium multi-processor SoC platform at first. Then we simulatethe 4 different topologies...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-to-all (broadcast) traffic can significantly degrade the performance of these designs, since they rely on multiple unicasts to provide one-to-many communication. This results in a burst of packets from a single source and is...
Video signal processing algorithms are characterized by high computational complexity and high memory throughput. Since the multicore architectures can provide high computational capacity and high throughput, they suit the video processing applications very well. However, it is very difficult to deal with the increasing design complexity and cost of the multicore system. For video processing application,...
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip networks is becoming critically important. These networks face unique design constraints and are required to provide extremely fast and high bandwidth communication, yet meet tight power and area budgets. In this paper, we present...
Three applications in wireless networks where model-free stochastic learning is applicable, are discussed. The learning based optimization problems are formulated and simulation results are presented. Some open issues are also discussed.
We designed and built a novel all-optical re-timing, re-amplifying, and re-shaping (3R) regeneration system based on terahertz optical asymmetric demultiplexers (TOADs) developed in our laboratory. The system is capable of parallel processing multiple wavelengths, a feature which will significantly improve the scalability of current wavelength division multiplexing (WDM) networks. Performance against...
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAMs, are shared between a multitude of IPs to satisfy these requirements at a low cost per bit. However, SDRAMs have highly variable access times that depend on previous requests. This makes it difficult to accurately and analytically...
A special round robin (RR) algorithm has been developed to equalize nickel metal hydride (NiMH) battery packs using a new selective equalizer. This algorithm detects batteries either at a very low state of charge (SOC) or at an extremely high SOC. In this system, a set of electromechanical relays are connected in a matrix to route boost current to the weaker batteries. The relay switching is controlled...
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