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This paper presents the synthesis of self-testing checker (STC) for a subset of l codewords of m-out-of-n code. We consider FPGA realization of the checker.
An innovative approach is utilized to design a remote access system to communicate with hardware design laboratories, called virtual laboratory (vLab). Through a server vLab provides multiple and concurrent accesses to FPGA design facilities in a laboratory located at Northern Illinois University. By using parallel communication channel (EPP) and MS Windows Remote Desktop (RDP) vLab is shown to provide...
The majority of encoder signal process circuits only support one type of the specific photoelectric encoder, either absolute encoder or incremental encoder. In order to realize the compatibility for both two types of encoders simultaneously, a novel encoder signal process circuit based on FPGA is presented in this paper. Firstly, a series of universal functions are analyzed and demonstrated. On this...
Soft-core processor's implemented on an FPGA are now days becoming very economical. These can be customized according to special needs and demands. Customization according to the application can be done using soft-core's. But there exists a lot of overhead in reimplementing and downloading the core again to the FPGA, if in case any changes are required in the code. Hence a new technique to overcome...
This paper presents the design of a distributed control system based on Hardware Petri nets with real time reconfigurable architecture. The system consists of a main computer unit and a lot of homogeneous reconfigurable controllers connected to a Wireless Local Area Network (WLAN). The control algorithm is implemented into an Field Programmable Gate Array (FPGA) circuit which is configured via a microcontroller...
Many companies and institutions employ packet filter firewalls in order to effectively regulate network traffic. Unfortunately, the constant growth of network bandwidth makes the task of matching packet headers against potentially large rulesets more difficult, and prohibits the sole use of entirely software-based firewalls which cannot cope with such huge amounts of traffic. Instead, high-speed firewalls...
The Discrete Fourier Transform (DFT) can be viewed as the Fourier Transform of a periodic and regularly sampled signal. The Non-Uniform Discrete Fourier Transform (NuDFT) is a generalization of the DFT for data that may not be regularly sampled in spatial or temporal dimensions. This flexibility allows for benefits in situation where sensor placement cannot be guaranteed to be regular or where prior...
Action recognition has been a research challenge in multimedia computing and machine vision. Recent advances in deep learning combined with stacked convolutional Independent Subspace Analysis (ISA) has achieved a better performance superior to all previously published results on several public available data sets. Unfortunately, one major issue in large-scale deployment of this new deep learning-based...
Mapping complex mathematical expressions to DSP blocks by relying on synthesis from pipelined code is inefficient and results in significantly reduced throughput. We have developed a tool to demonstrate the benefit of considering the structure and pipeline arrangement of the DSP block in mapping of functions. Implementations where the structure of the DSP block is considered during pipelining achieve...
The Research Centre Juelich is developing a PET detector for plant phenotyping together with Philips Digital Photon Counting, Aachen. The scientific goal is to study the carbon transport in plants. To detect the photon pairs we use a ring of digital photon counters recently developed by Philips. For the prototype we decided to use a Xilinx Kintex evaluation board for data concentration and processing...
At present there are various measuring devices or instruments that acquire the electrical activity of the heart (ECGs), but make a proper measurement, models the signs are printed directly on sheets of graph paper, unable to save the information for later analysis. In this work we make the development of a bioelectric signal acquisition, in this case focused on the signals emitted by the heart to...
Digital systems capable of altering their hardware configuration on the fly are labeled dynamically reconfigurable. Proteus is an OpenRISC-based computer optimized for Xilinx's FPGAs that can dynamically reconfigure itself. Proteus was conceived as a platform to facilitate the study of reconfigurable computing architectures by providing a turn-key solution that is openly available. This paper describes...
The computational demands on spacecraft are rapidly increasing. Current on-board computing components and architectures cannot keep up with the growing requirements. Only a small selection of space-qualified processors and FPGAs are available and current architectures stick with the inflexible cold-redundant structure. The objective of the ongoing project OBC-NG (On-board Computer - Next Generation)...
Nowadays, there is a rapid introduction of new digital technologies. These technologies offer exciting and new opportunities that can increase the connectivity of devices within the home for the purpose of home automation. Here, we present the design and implementation of home automation system. The design is described using VHDL (VHSIC Hardware Description Language) and implemented using hardware...
The detection of moving object is fundamental to automated video surveillance, object analysis and recognition. It involves the trajectory of an object over time by locating its position in every frame of the video. In this paper we implement a moving object detection method on FPGA. Detection of moving object is a challenging task. In our implementation of the design we used the background subtraction...
We study the performance and energy characteristics of a reconfigurable active solid-state drive (RASSD) consisting of a tightly-coupled FPGA/SSD pair. The FPGA implements a compute node that uses partial dynamic reconfiguration to implement hardware accelerators that process data streaming from the SSD. Using K-means clustering as a representative data analytics workload, we show that a RASSD node...
Parallel processing is a complex topic found in computing education and has become an essential topic in the curricula owing to the recent developments in both software and hardware. Ensuring access to parallel computers in order to provide a better education at universities is not guaranteed due to the high cost of these devices. Alternatively, parallel processing can be taught using simulators....
To meet the need of signal acquisition for Digital Radio Mondiale (DRM) equipment in communication security application, an embedded system is set up by combing signal acquisition and decoding module, host computer monitor module and PC104 bus control module, taking advantage of high data transmission efficiency on PC104 bus. Signal data is acquired and decoded by signal acquisition and decoding module...
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