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Networks on Chip (NoC) has been widely discussed for its smart structure and high performance. Routing algorithms significantly influence design cost and system performance of NoC. In this paper, a new hardware method called Final-Destination-Tag (FDT) is proposed to improve the original Destination-Tag (DT) method for implementing different routing algorithms. Compared with the DT method, the proposed...
A small-granularity solution with high performance and low area cost for fault-tolerant routing of hard error in 2D-Mesh Network-on-Chip is proposed. This solution presents a new fault model, defines separately node-fault and link-fault, reduces situations classified as node-fault effectively, and consequently improves the performance of the network. By defining some new paths to substitute failure...
In a delay tolerant network (DTN), nodes are connected intermittently and the future node connections are mostly unknown. Since in these networks, a fully connected path from source to destination is unlikely to exist, message delivery relies on opportunistic routing. However, effective forwarding based on a limited knowledge of contact behavior of nodes is challenging. Most of the previous studies...
Routability is a mandatory metric for modern large-scale mixed-size circuit placement which typically needs to handle hundreds of large macros and millions of small standard cells. However, most existing academic mixed-size placers either focus on wirelength minimization alone, or do not consider the impact of movable macros on routing. To remedy these insufficiencies, this paper formulates design-hierarchy...
Electrowetting-on-dielectric (EWOD) chips have emerged as the most widely used actuators for digital microfluidic (DMF) systems. These devices enable the electrical manipulation of microfluidics with various advantages such as low power consumption, flexibility, accuracy, and efficiency. In addressing the need for low-cost and practical fabrication, pin-count reduction has become a key problem to...
Delay Tolerant Networks (DTN) is a kind of sparse Ad Hoc networks in which no contemporaneous path exists between any two nodes most of the time. Multicasting in DTN is a desirable feature for applications where some form of group communication is in demand. In this paper, we propose a multicast protocol for DTN: ECAM (Epidemic-based Controlled Flooding and Adaptive Multicast for Delay Tolerant Networks)...
Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are easy to catch transmission errors due to DSM noise. A comprehensive fault-tolerant mechanism for transient and permanent failures is proposed in this paper. Based on the special NoC with a network monitor, a flit level point-to-point error detection scheme is added...
Unlike traditional routing schemes that route all traffic along a single path, multipath routing strategies split the traffic among several paths in order to ease congestion. It has been widely recognized that multipath routing can be fundamentally more efficient than the traditional approach of routing along single paths. aiming at the increasing network traffic and the deficity that the former Ant...
Efficient on-chip communication is very important for exploiting enormous computing power available on a multi-core chip. Network on Chip (NoC) has emerged as a competitive candidate for implementing on-chip communication. Routing algorithms significantly affect the performance of a NoC. Most of the existing NoC architectural proposals advocate distributed routing algorithms for building NoC platforms...
Network-on-chip (NoC) is being proposed as a scalable and reusable communication platform for future embedded systems. The performance of NoC largely depends on the underlying deadlock-free and efficient routing algorithm. When the adaptive routing returns a set of acceptable output channels, then a selection strategy is used to select the output channel, therefore the selection strategy affects the...
As technology advances, the number of cores in Chip Multi Processor systems (CMPs) and Multi Processor Systems-on-Chips (MPSoCs) keeps increasing. Current test chips and products reach tens of cores, and it is expected to reach hundreds of cores in the near future. Such complexity demands for an efficient network-on-chip (NoC). The common choice to build such networks is the 2D mesh topology (as it...
Although adaptive routing algorithms promise higher communication performance, as compared to deterministic routing algorithms, they suffer from the out-of-order packet delivery problem. In the context of Network on Chip, the area and computational overhead of ordering packets at the destination is high and may reverse any gain achieved through the use of adaptivity of the routing algorithm. In this...
Flow control in Network on Chip (NoC) is critical because unbalanced transmission process and congestion in nodes can affect on-chip performance: communication latency, throughput and heat accumulation. To achieve the goal to balance on-chip communication load, we present a distributed routing scheme named RIPNoC (Router Information Piggybacking Routing Scheme for NoC). This routing scheme provides...
Several NoC routing schemes proposals targeting overall performance optimization are available in the literature. However, such proposals do not differentiate the application flows. The goal here is to demonstrate that adaptive routing algorithms can be used in flows with temporal constraints, enabling an enhanced degree of path exploration. The main contribution of this work is to expose the routing...
With the increase of communications between lots of cores, traditional unicast communication is not enough to satisfy on-chip application requirements . Multicast communication rarely considered in NoC, can ease the resource burden, use the bandwidth efficiently in order to achieve cache coherency protocol to support faster and more efficient collective communication. Several typical multicast routing...
Traditional single-next-hop routing algorithms always chose the best path to routing, which often brought transport congestion. It can not sufficiently utilize network resource and can not flexibly distribute traffic. Compared to the traditional single-next hop routing, multi-next hop routing have more advantages. It can implement packets forwarding in parallel, while preserves the best-effort model...
A new deadlock-free dynamic routing algorithm is proposed for wormhole-switched network-on-chip. Introducing the concept of multilevel congestion-aware mechanism which conveys more accurate feedback information about network congestion status than the DyAD routing, the proposed algorithm adopt proper routing algorithm to forward packets according to the current congestion level. Simulation results...
Recently, a Network on Chip (NoC) has attracted much attention for its smart structure and high performance. However, NoC routing algorithms significantly influences the performance and design cost. In this paper, a new hardware method to implement a routing algorithm is proposed. The proposed method is used to replace the general destination-tag method for router design. We simulate and evaluate...
In a Multi-Processor System-on-Chip (MPSoC)-based embedded system with Network-on-chip (NoC) as the communication architecture, routing of the communication traffic among the Processing Elements (PEs) contributes significantly to the overall latency, throughput and energy consumption. Design of an efficient routing algorithm for NoC requires a thorough understanding of the role of individual components...
Network-on-chip (NoC) architectures have been recently proposed as the communication framework for large-scale chips. The design of the routing system for the packet-switched on-chip network is one of the critical issues for the success of NoC architectures, especially when there are faulty components in the network. In this paper, we present a routing technique that uses an embedded tree for mesh...
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