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The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
Multi-core SoC created great opportunities to increase overall system performance while keeping the power in check but also created many design challenges that designers must now overcome. The challenge of doubling performance every two years used to drive superscalar design with more functional units running concurrently or deeper pipeline racing for highest frequency at the cost of higher power...
In this paper, an operational transconductane amplifier (OTA) with tunable transconductance and threshold level, based on multiple input floating gate MOS (MIFGMOS) transistor is presented. This OTA has much wider linear range compared to CMOS based OTA. This circuit is suitable for analog signal processing and neural network applications. It can be used as neuron activation function (NAF) with programmable...
Results on fabrication and DC-characterisation of vertical InAs nano-wire wrap-gate field-effect transistor arrays with a gate length of 50 nm are presented. Each nanowire array was processed into a transistor with a systematic variation in a number of wires and wire diameter over the sample. Extensive studies have been performed on the influence of wire number and diameter on the transistor characteristics...
Technology scaling has entered a new era, where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate the choice of technology, and architecture, and dictate the use of implementation techniques that trade off performance for power savings. This paper examines the technology options in the power-limited scaling regime,...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
This paper will present a very compact EEPROM cell for high density applications, featuring split voltage programming. The information is stored in a self-aligned floating-gate transistor with thin (8nm) tunnel oxide. Bit selection is performed by a low-voltage transitor. Long endurance (more than 106 cycles) is achieved and the asymmetric window closing will be explained. The innovative cell concept...
A new high-density memory cell concept for storing analog information as well as digital data is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor generates a large bit-line signal voltage at a supply voltage as low as 1.0V. Since this cell does not need a large storage capacitance and the pass-transistor can be stacked on the top of the amplifying...
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