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We propose a multi-voltage (multi-Vdd) variable pipeline router to reduce the power consumption of Network-on-Chips (NoCs) designed for chip multi-processors (CMPs). Our multi-Vdd variable pipeline router adjusts its pipeline depth (i.e., communication latency) and supply voltage level in response to the applied workload. Unlike dynamic voltage and frequency scaling (DVFS) routers, the operating frequency...
This paper proposes a battery life time extension method which maximizes the efficiency of a battery by monitoring the available capacity of smartphone battery and by controlling the time interval for the transmission signalling of SNS application. The proposed method extends the battery life time by operating on saving mode which delays the process of sending background traffic if the battery capacity...
Cloud computing and Virtualization has become the focus of tremendous amount of research in recent years. The advances in network bandwidth, the need for services that can be accessed anytime from anywhere and the change in ownership models are some of the factors responsible. As cloud services are intended to be ‘always on’, the energy costs to provision services are already significant with increase...
Dynamic Application Hosting Management (DAHM) allows clouds to dynamically host applications in data centers at different locations based on: (i) spatio-temporal variation of energy price, (ii) data center computing and cooling energy efficiency, (iii) Virtual Machine (VM) migration cost for the applications, and (iv) any SLA violations due to migration overhead or network delay. DAHM is complementary...
This paper deals with the design and analysis of 1Kb Static Random Access Memory (SRAM) at 180nm, focusing on optimizing power and delay. The entire SRAM can be divided into 4 blocks with each block having equal capacity of 256b. The key of low power operation in the SRAM is to reduce the wordline capacitance. The sense amplifier is placed below the column decoder circuit. Here only one sense amplifier...
Multicore architectures with multilevel caches are being used in both desktop and embedded processors for their improved performance. Caches increase execution time unpredictability and make it difficult to support real-time applications. Caches also challenge the power supply system by consuming a lot of power. Studies show that cache locking improves predictability and performance/power ratio for...
Although cache improves performance by reducing the speed-gap between the CPU and main memory, cache increases the timing unpredictability due to its dynamic nature. Cache also requires significant amount of power to be operated. Unpredictability and power consumption become even worse in multicore systems due the presence of multiple levels of caches. Recent studies indicate that predictability can...
High-performance Low-power static random access memories (SRAMs) are required in many battery-powered applications. This paper presents a process temperature frequency (PTF) adaptive voltage scale technique to reduce power. In the self-adaption phase, the optimal supply voltage is chose automatically according to PTF. So a significant reduction in power consumption can be achieved. Moreover, SRAMs...
Interest in on-line error detection continues to grow as VLSI circuits increase in complexity. Concurrent checking is increasingly becoming a desirable characteristic thanks to its ability to detect transient faults that may occur in a circuit during normal operation. Accordingly, Concurrent Error Detection (CED) techniques allow the detection of transient faults, which probably not be detected in...
In this paper, we have proposed a new SRAM cell architecture which consists of an asymmetric inverter pair to reduce the power consumption. In this work, we reduced the power and delay during write operation by a significant amount. However the area will be increased slightly. The average power consumption in SRAM cell is reduced by about 65.50% during a write operation and reduction in write delay...
In this paper, we present a method for creating LDPC codes which are specifically designed to be hardware friendly. Our method involves constraining the cyclic shift values in the base H-matrix to reduce the complexity of the cyclic shift hardware. We show that the decoder hardware implementation for these codes has higher throughput and lower power consumption than decoders designed for traditional...
This paper presents a novel CMOS 6-transistor SRAM cell for different purposes including low power embedded SRAM applications and stand-alone SRAM applications. The data is retained by the cell with the help of leakage current and positive feedback, and does not use any refresh cycle. The size of the new cell is comparable to the conventional six-transistor cell of same technology and design rules...
Abstract-For multi-homed streaming service, it is important to enhance the throughput by efficient allocation of resources to the most appropriate interfaces of the User Terminal (UT). However, running multiple interfaces simultaneously can significantly contribute to rapid reduction of battery life. In this work, we propose a Power Minimized Rate Allocation Scheme (PMRAS) with optimal rate allocation...
Optimization of circuits to reduce power consumption is more and more important. Techniques to reduce power at architectural level are not sufficient to minimize the impact of power consumption in modern designs, using nano CMOS technologies. Classical standard cells methodology is widely used in digital designs. However it is far away of power optimization at physical design level. It is becoming...
The interest in non-synchronous design of digital circuits is growing due to technology scaling into deep submicron transistor geometries and to the problems this scaling causes to keep synchronous design advantageous. To enable most non-synchronous styles, the C-element is a fundamental device that has to be available as logic primitive. A recently proposed design flow improved a standard cell library,...
We introduce a new logic style called Pseudo-Static Current Mode Logic (PSCML), which aims to alleviate the power consumption and delay overhead concerns that have thwarted the wide-spread acceptance of a previously proposed Dynamic Current Mode Logic (DyCML) style. Different from DyCML, the proposed new logic style may be viewed by its environment as static, hence any PSCML-based gate/module can...
In this paper, we exploit the ambipolarity property of double gate devices such as DG-CNTFETs to design a new 4:1 multiplexer, with a significant reduction in circuit complexity with respect to conventional CMOS-based multiplexers for equivalent functionality. Based on Pass-Transistor Logic, it demonstrates performance improvement of up to 3× concerning Power-Delay-Product reduction, as compared to...
Topology has significant effects on the most important parameters of a network such as latency and power consumption. The sphere based topology is a new structure for Network-on-Chips that forms in sphere shape. We have used a Zone-Order label based algorithm for the routing that is a general algorithm for routing requirements, and it is based on spanning tree. We have compared sphere based topology...
A glitch compensation methodology is proposed in this paper which involves in reducing the undesired switching of combinational circuits in order to save dynamic power. The proposed methodology can be seamlessly integrated to existing physical design flow. A glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits when differential delay...
The paper presents a new design for implementing a static Master-Slave Flip-flop with reduced transistor count for low power and high performance applications. The proposed flip-flop is realized using only eleven transistors (including an inverter to produce complementary clock signals locally) hence reducing the manufacturing cost. SPICE simulation results at a frequency of 250 MHz using 180 nm/1...
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