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Due to the increasing opportunities for malicious inclusions in hardware, Design-for-Trust (DFTr) is emerging as an important IC design methodology. In order to incorporate the DFTr techniques into the IC development cycle, they have to be practical in terms of their Trojan detection capabilities, hardware overhead, and test cost. We propose a non-invasive DFTr technique, which can detect Trojans...
In this paper, we propose an area and power efficient pipeline FFT processor for 8×8 MIMO-OFDM systems. The proposed FFT processor is based on mixed-radix multipath delay commutator (MRMDC) architecture in terms of low complexity and high memory utilization. A conventional MRMDC FFT processor increases hardware scale due to delay commutators which are used to change the order of the input sequences...
This paper presents a novel eight-parallel 128/256-point mixed-radix multi-path delay commutator (MRMDC) FFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed FFT architecture can provide a higher throughput rate and low hardware complexity by using an eight-parallel data-path scheme, a multi-path delay commutator structure and an efficient scheduling scheme of...
Fast multiplication can be achieved by using canonical signed digit (CSD) to speed-up computations. Conversion to CSD is needed when the multiplier is not known a priori. In this work, a novel approach for converting an unsigned binary number or two's complement number to its CSD form from least significant bit to most significant bit, (right-to-left), is presented. Comparison shows that our algorithm...
A novel spike-based computation architecture has been developed which represents synaptic weights in time. An analog chip with 32 neurons, 1024 synapses and an AER block has been fabricated in 0.5µm technology. A digital implementation of the architecture having 6,144 neurons and 100,352 synapses on an FPGA is also described. A digital controller for routing spikes can processes up to 34 million synapses...
This paper presents the implementation and experimental evaluation of a MAC protocol designed to overcome some of the limitations of affordable and widely-deployed software defined radio hardware. We propose a modified Aloha-based MAC protocol with implicit acknowledgements to mitigate the impact of intra-flow collisions in multi-hop wireless communications. We experimentally observe a significant...
An area-efficient diminished-1 modulo 2n+1 multiplier with radix-4 modified Booth encoding is proposed. The proposed approach minimizes the number of Booth encoder and Booth decoder blocks required for partial product generation. Its correction factor is decomposed into a multiplier-dependent dynamic bias and a multiplier-independent static bias. The dynamic bias can be generated by hardwiring the...
A hybrid radix-4/-8 multiplier is proposed for portable multimedia applications that demand high speed and low energy operation. Depending on the input pattern, the multiplier operates in the radix-8 mode in 56% of the input cases for low power, but reverts to the radix-4 mode in 44% of the slower input cases for high speed. For this, a mode detection circuit determines the mode signal from the input...
In this paper we discuss a cognitive radio architecture based on sub-Nyquist sampling scheme. At present, analog-to-digital converters can process wide-band signals up to 1GHz and therefore convert it into the digital baseband. To deal with the limited processing power a multicoset sampling filter in the digital domain is introduced. Thus, it is possible to have a fully flexible multiband filter for...
This paper proposes an ultra low energy FFT processor suitable for sensor applications. The processor is based on R4MDC but achieves full utilization of computational elements. It has two parallel datapaths that increase throughput by a factor of 2 and also enable high memory utilization. The proposed design is implemented in 65nm CMOS technology and post-layout simulation including parasitic capacitances...
This paper investigates the potential of emerging asynchronous quasi delay insensitive (a-QDI) logic devices for the realization of high-speed low-power 2D infinite impulse response digital beam filters. Recently proposed raster-scanned hardware architectures based on direct-form I and wave-digital realization are extended to clock-free asynchronous logic using state-of-the-art asynchronous field...
Multi-Processor System on Chip (MPSoC) platform plays a vital role in parallel processor architecture design. However, it poses a great challenge to design a flexible high-speed network regarding as the growing number of processors. This paper proposes a star network based on peer to peer links on FPGA. The stat network uses fast simplex links (FSL) for demonstration to connect scheduler and processing...
A system-level model for an analog-to-digital converter (ADC) is described. The main functions of the ADC are identified, then mapped into functional units to give a holistic view of the ADC's behavior and more importantly, what the critical parameters are, and the main sources of errors. A trade off between high and low abstraction level is taken into consideration. The model is independent from...
The specifications of the control units driving embedded systems often involve temporal properties. We aim at certifying them statically using the Abstract Interpretation framework and introduce several Abstract Domains dedicated to proving such temporal properties. This work defines the specificity of such domains, that we call Temporal Abstract Domains. We introduce a continuous-time abstraction,...
In this paper, we propose a high-performance logarithmic converter using novel two-region bit-level manipulation schemes. The proposed technique provides an area-time-efficient hardware implementation, since it avoids the need of a ROM by using simple arithmetic operations instead. Accuracy analysis shows that the proposed converter can achieve an error range and percent error range of only 0.0319...
In this paper, an efficient method for high speed hardware implementation of AES algorithm is presented. So far, many implementations of AES have been proposed, for various goals that effect the SubByte transformation in various ways. These methods of implementation are based on combinational logic and are done in polynomial bases. In the proposed architecture, it is done by using composite field...
Cognitive radio has been put forward to make efficient use of scarce radio frequency spectrum. Spectrum sensing is the cornerstone of cognitive radio. As a part of the effort toward building a cognitive radio network testbed, we have demonstrated real-time spectrum sensing. However, current hardware platforms for cognitive radio introduce time delays that actually undermine the accuracy of spectrum...
In this paper, we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentially sin/cos, sinh/cosh and arctan computation. In our proposed architecture, radix-2 arithmetic is employed. The design targets real time...
We propose an efficient implementation of Monte Carlo based statistical static timing analysis (MC-SSTA) on FPGAs. MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference because of its ability to handle any timing distributions and correlations. Extremely long CPU time has been required for the MC-SSTA, which...
Various commercial and academic tools are available for the synthesis of hardware algorithms. Focusing on signal processing algorithms, we compare efficiency, flexibility and usability of hardware synthesis approaches based on the widely used Matlab with add-on toolboxes or 3rd-party tools. We use several designs as case studies to investigate the effect of the tool features with respect to hardware...
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