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Ring oscillators are commonly used as a locking mechanism that binds a hardware design to a specific area of silicon within an integrated circuit (IC). This locking mechanism can be used to detect malicious modifications to the hardware design, also known as a hardware Trojan, in situations where such modifications result in a change to the physical placement of the design on the IC. However, careful...
This paper presents some power results of Joint Photographic Experts Group (JPEG) in Field-Programmable Gate Array (FPGA) and provides some analysis and results in reduced dynamics-power methods of it. The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and payload capacitance. We use Xilinx XPower Analyzer to analyze the impact of different switching...
Hardware Trojans have become a growing concern in the design of secure integrated circuits. In this work, we present a set of novel hardware Trojans aimed at evading detection methods, designed as part of the CSAW Embedded System Challenge 2010. We introduced and implemented unique Trojans based on side-channel analysis that leak the secret key in the reference encryption algorithm. These side-channel-based...
The increasing development of configurable electronic systems for digital processing of signals from radiation detectors highlights the convenience of having more and more advanced equipment for support design and test of processing architectures from the hardware and firmware point of view. We propose a configurable design and test equipment that is able to emulate the detection process output on...
This paper presents a framework for signal-level emulation of propagation effects over generalized fading channels at the scale of entire networks. Network emulation enables research into network- scale systems - which would otherwise be limited to low-fidelity network simulators and one-off field experiments - to use real radio hardware and realistic channel models. Our hardware and software architecture...
This paper presents a multi-channel Digital Programmable Delay Trigger System (DPDTS) with high accuracy and wide delay range, which can be widely used in laser system and electron accelerator. This DPDTS mainly makes up of reference clock module, user interface and control module and Digital Programmable Delay Trigger (DPDT) module which is implemented on a Xilinx V6LX75T FPGA. In this DPDTS, DDS...
In the radio channel, compression is used for transmission of real-time analog video signal and compressed bits can usually be transmitted at a non-constant rate. But standard video can be displayed on TV at a constant rate. It is difficult to decode the intermittent compressed data for real-time video display. In order to solve the problem which rate of video decoding and compressed bits in the radio...
A hardware-based solution of precise time synchronization over Ethernet was proposed for Networked Control System (NCS). Using Field-programmable Gate Array (FPGA), hardware-based solution was designed for implementing time synchronization protocol defined in IEEE 1588. Timestamp capture, oscillator frequency compensation, time synchronization and etc., were all coded with Very High Speed Integrated...
This paper presents a reconfigurable mechanism for the multiplier. The proposed mechanism is applied to generate a multiplier, whose data width, type and pipeline depth can be customized. The data width of each operand of these generated multipliers can be configured for 4i where i=1, 2, 3, 4, 5, 6, 7, 8. And the data type of operand can be unsigned or signed at will. The multiplier is composed of...
A novel digital delay generator (DDG) based on FPGA was designed with 4.4ms range and 65ps resolution. The time-to-digital conversion (TDC) utilizing dual tapped delay lines was implemented in the FPGA to accurately measure the time interval between the rising edge of the FPGA global clock and the input trigger pulse. And the time interval was compensated in the following circuits by a AD9501 chip...
The study in this paper is aimed at improving the performance of a network processor design (XDNP) based on a Virtex-4 FPGA by using the PlanAhead tool offered by XILINX. PlanAhead gives a unique visibility into the design. The tool can very quickly identify the critical path, and then supply hierarchical floorplanning to achieve faster timing closure. XDNP is targeted at networking applications requiring...
This paper presents a multi-function multi-GHz test module designed to enhance the performance capabilities of automatic test equipment (ATE). The test module is designed with a core logic block consisting of a high-performance FPGA. It also contains an application specific logic block that is designed to perform multiple functions not possible with the FPGA alone. We demonstrate five applications:...
Although measurement methods for Electromagnetic (EM) immunity and Total Ionizing Dose (TID) radiation are highly standardized, no effort has been made to evaluate the behavior of embedded systems under the combined effects. Considering realistic environment conditions only the measurement of these effects can guarantee reliable embedded systems for critical applications. A configurable platform to...
SET propagation and mitigation in 65-nm test structures are investigated. Radiation tests show a clear distortion of the SET pulse-widths related to the structures' design and layout and the efficacy of the employed mitigation techniques.
Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are employed such as building fast multipliers. Most fast multiplier architectures use some form of a Carry Save Adder (CSA) Tree, which is also called Column Compression (CC). We propose...
In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices — amount of FPGA resources used and maximum delay,...
In high frequency FPGAs with technology scale shrinking and threshold voltage value decreasing and based on existing large numbers of unused resources, leakage power has a considerable contribution in total power consumption. On the other hand, process variation, as an important challenge in nano-scale technologies, has a great impact on leakage power of FPGAs. Reconfigurability of FPGAs makes an...
Arithmetic operations in digital signal processing applications suffer from problems including propagation delay and circuit complexity. QSD number representation allows a method of fast addition/subtraction because the carry propagation chains are eliminated and hence it reduces the propagation time in comparison with common radix 2 system. Here we propose an arithmetic unit based on QSD number system...
Devadas has first proposed the notion of Silicon Physical Unclonable Function (sPUF), which takes advantage of delay variations of wires and gates. A Ring-Oscillator-Based PUF (RO PUF) is one possible implementation of an sPUF. One disadvantage of RO PUFs is that they require one pair of ring oscillators per bit of output. Therefore, in order to collect enough output bits for a safe security level,...
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