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Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient transistor-level modification to significantly reduce the area and power of the CSLA. Based on this modification...
In nano-scale digital CMOS ICs, technology parameter variation limits the usefulness of traditional corner-based timing simulation in favor of statistical simulation. Yet, logic level delay modeling featuring technology variation aware timing is an open challenge. We present a new semi-empirical delay model of digital CMOS cells, accounting for input slope and technology parameters, featuring Spice-level...
Pulsed bias is an innovative technique introduced to improve the performance of oscillators in integrated circuits and is based on recent development of Floquet eigenvectors theory. Given the relatively low value of resonator quality factor achievable on-chip, for a specified bias voltage level, pulsed bias may result in a lower power consumption and in an improvement of the spectral purity of the...
The growing demand for ultra low power applications has drawn interest in low voltage digital circuits, operating in the near-threshold region. Asynchronous circuits, operating with near-threshold supply voltages, are more attractive than their synchronous counterparts due to higher resilience to PVT variations. This paper presents a novel ultra-low power C-element, which is a basic building block...
Voltage reduction is a very widely used low-power technique (as reducing dynamic power quadratically, and leakage power linearly) which does sacrifice performance. An alternate technique, which is much less explored/investigated, is to rely on currents instead. The paper presents a thorough but still preliminary comparison of a recently introduced CMOS design technique which limits/reduces currents,...
In this paper we present a novel ultra-low-voltage (ULV) CMOS flip-flop. The ULV flip-flop offers increased speed compared to other FF's for low supply voltages. The pulse generator (PG) circuit in a conventional sense amplifier SAFF is replaced by a high-speed tristate edge generator (EG) with a rise- and fall-time less than 1/10 of an inverter operating with the same supply voltage. In essence the...
Soft errors induced by radiation, causing malfunctions in electronic systems and circuits, have become one of the most challenging issues that impact the reliability of the modern processors even in sea-level applications. In this paper we present two novel radiation-hardening techniques at Gate-level. We present a Single-Event-Upset (SEU) tolerant Flip-Flop design with 38% less power overhead and...
A 7GHz-clock 1mV-input-resolution comparator is designed and simulated in a 65nm CMOS process. The comparator offset is compensated by changing the body voltages of the input differential triple-well NFET transistor pair. A reset switch is added between two regeneration nodes to further match voltages in reset phase. Kickback noise in this comparator is reduced by isolating regeneration nodes of the...
A new active LO phase shifter is introduced and implemented in a 2×2 MIMO receiver using STMicroelectronics 90nm CMOS technology. One of the advantaged of this new phase shifter is its capability of achieving very high resolution phase shifting over a wide range of frequencies which makes it suitable for multi-standard wireless applications. The proposed phase shifter is fully transistor based and...
The power optimization of integrated circuits must be observed in all levels of abstraction of the design flow. The traditional standard cell flow don't really takes care of power minimization at physical level, because there is a limited number of logical functions in a cell library, as well a limited number of sizing versions. To really obtain an optimization at physical level, it is needed to allow...
We present an implementation of a programmable axonal propagation delay circuit which uses one first-order log-domain low-pass filter. Delays may be programmed in the 5–50ms range. It is designed to be a building block for time-delay spiking neural networks. It consists of a leaky-integrate-and-fire core, a spike generator circuit, and a delay adaptation circuit.
In this paper, a new XOR gate and architecture for parallel calculation of CRC and DBI are proposed. With this proposal, speed constraints in high-speed DRAMs such as GDDR5 and DDR4 SDRAM are relaxed. This helps minimize the latency increase and hence the effective bandwidth loss from CRC and DBI functions.
Near-threshold (NT) FFs, which operate from a supply voltage close to the transistor threshold voltage, are considered as a good alternative for portable applications, where low power dissipation with reasonable performance is the main demand. This paper presents an improved model for delay/energy estimation of the NT FFs. The proposed model, based on the EKV current and alpha power law models, improves...
Delay elements are used in integrated circuits (ICs) to meet design specific timing requirements. Delays are often generated by increasing the input transition times. For long delays, such a signal generally results in prolonged short-circuit current either within the delay element itself or at the subsequent stage, elevating the overall power consumption of the system. In this paper, a novel CMOS...
Unlike static CMOS circuits, the standby energy in sense amplifier-based pass transistor logic (SAPTL) circuits can be decoupled from its performance, allowing separate optimization strategies for leakage and speed. In this paper, a 64-byte parallel cyclic-redundancy check (CRC) generator is designed and implemented using asynchronous 90nm SAPTL circuits, with a simulated minimum energy point that...
We propose a robust asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic (SAPTL) approach with improved speed and power attributes over reported SAPTL approach. These attributes are achieved by simplifying various sub-blocks therein to reduce the stacking of pass transistors and the number of transistor switchings, and to avoid floating nodes. By means of an 8-bit pipeline adder...
In this paper we show that, when dealing with transmission-gate based Master-Slave FFs, a reconsideration of the usual approach for high-speed design is worthwhile to improve energy-efficiency. By splitting such FFs in two separately optimized sections and then reconciling the results, the emerging design always outperforms that resulting from the employment of a classical procedure assuming FFs as...
A low leakage memory is an indispensable part of any sensor application that spends significant time in standby (sleep) mode. Although using high Vth (HVT) devices is the most straightforward way to reduce leakage, it also limits operation speed during active mode. In this paper, a low leakage 10T SRAM cell, which compensates for operation speed using a readily available secondary supply, is proposed...
This paper presents a new technique to accurately measure the data retention voltage (DRV) of large SRAM arrays in the presence of process variations. The proposed technique relies on a built-in-self-test (BIST) unit along with a DC-DC converter. The BIST unit implements a modified version of the March C- test that accounts for data retention faults. Whereas, the DC-DC converter is used to scale down...
Dual edge triggered flip flops has twice the throughput, so they can be run at half the frequency to reduce power consumption at the clock distribution network. Three Dual edge flips were compared with each other. C-DDR-FF has the lowest power consumption due to its' very simple structure, Ep-dsff has the lowest area due to the sharing of the clock pulse generator, while CBS-FF has the fastest speed...
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