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This paper is concerned with the generalized H2 filtering problem of static neural networks with time-varying delay. A delay-dependent design criterion with less conservatism is derived by employing the reciprocally convex combination technique. It is shown that the gain matrix and the optimal generalized H2 performance index can be simultaneously obtained by solving a convex optimization problem...
The Internet architecture provides a mechanism for protecting individual flows from congestion, by introducing queue management and scheduling algorithms in Input-Queued switches having finite queue size to improve the QoS performance in terms of throughput and delay. Queue management algorithms manage the length of packet queues by dropping packets when necessary or appropriate, while Scheduling...
Clock skew scheduling is an efficient technique to minimize the cycle period by properly assigning clock delays to registers in a circuit. But its effectiveness is limited by the difficulty in implementing a large number of arbitrary clock skews. Multi-domain clock skew scheduling and prescribed-domain clock skew scheduling are two alternatives to overcome this shortage by restricting the number of...
Low power has become a burning issue in modern VLSI design. To deal with this problem, the multiple-supply voltage (MSV) is a technique widely applied to a design to reduce its power consumption. However, there exist several challenges in implementing Multi-Voltage designs, which includes floorplanning, level-shifter placement, and power planning [5]. Among these challenges, placement of level shifters...
MIL-STD-1553 is a protocol for a communication network, the life-line of aircrafts, space vehicles and unmanned aerial vehicles (UAVs) etc., on which the command and control computer and all the embedded Avionics subsystems of the platform are interconnected. The 1553 system integrator has to ensure that the defined limits of the 1553 standard for maximum bus loading and delay ratios are met for all...
Mapping into K-input lookup tables (K-LUTs) is an important step in synthesis for Field-Programmable Gate Arrays (FPGAs). The traditional FPGA architecture assumes all interconnects between individual LUTs are “routable”. This paper proposes a modified FPGA architecture which allows for direct (non-routable) connections between adjacent LUTs. As a result, delay can be reduced but area may increase...
Network-on-Chip (NoC) architectures have emerged as a better replacement of the traditional bus-based communication in the many-core era. However, continuous technology scaling has made aging mechanisms such as Negative Bias Temperature Instability (NBTI) and electromigration primary concerns in NoC design. In this paper1, we propose a novel system-level aging model to model the effects of asymmetric...
In this paper, we propose the network traffic mitigation method using TCP signalling delay algorithm. By using proposed method, the TCP signalling response time is adjusted according to network traffic load status. Through the queuing analysis, we verify that the network traffic load can be mitigated.
This paper is concerned with network-based static output feedback tracking control for a class of systems that can not be stabilized by a static output feedback controller without a time-delay, but can be stabilized by a delayed static output feedback controller. For such systems, a stable and satisfactory tracking control can be achieved by intentionally introducing bounded network-induced delays...
In this paper we extend and analyze the distributed dual averaging algorithm [1] to handle communication delays and general stochastic consensus protocols. Assuming each network link experiences some fixed bounded delay, we show that distributed dual averaging converges and the error decays at a rate O(T−0.5) where T is the number of iterations. This bound is an improvement over [1] by a logarithmic...
This paper investigates the influence of chronotype and social zeitgebers on circadian rhythm using an accelerometer-based sensor network. Participants with different chronotypes (i.e., morning types and evening types) were recruited to participate in this study. Chronotype was determined by participant responses to the Morningness-Eveningess Questionnaire (MEQ). A wearable accelerometer-based sensor...
This paper presents a system for automating sound synthesis parameters during live musical performances. It is a novel practical solution for keyboard players who need to manually control numerous synthesis parameters while playing at the same time. Our idea was to let musicians define how parameters will change through time by inserting automation data into a prerecorded musical piece. During a live...
The most timing critical part of logic design usually contains one or more arithmetic operations, in which addition is commonly involved. The carry-skip adder, which is designed to reduce the time needed to propagate the carry by skipping over groups of consecutive adder stages, is known to be comparable in speed to the carry look-ahead technique while it uses less logic area and less power. Nevertheless,...
We developed a new post-synthesis algorithm that minimizes leakage power while strictly preserving the delay constraint. A key aspect of the approach is a new threshold voltage (VT) assignment algorithm that employs a cost function that is globally aware of the entire circuit. Thresholds are first raised as much as possible subject to the delay constraint. To further reduce leakage, the delay constraint...
Dynamic Partial Reconfiguration (DPR) on FPGAs has attracted significant research interests in recent years since it provides benefits such as reduced area and flexible functionality. However, due to the lack of supporting synthesis tools in current DPR design flow, leveraging these benefits requires specific designer expertise with laborious manual design effort. Considering the complicated concurrency...
With a large number of different standards of sample rates we often need to use sample rate conversion algorithms. If the resampling ratio is not expressed as the ratio of small integer numbers or is not a fixed value, the sample rate conversion algorithm based on fractional delay filters might be used since it allows for arbitrary resampling ratios. The performance of such algorithm depends solely...
Distributed algorithms discussed in this paper provide a better performance than other well known algorithms designed for detecting deadlock, with respect to the communication bus load and fault tolerance, while the same assumptions for the operating conditions are preserved. Several concepts are defined for a group of deadlocked distributed tasks: probe messages, propagation law of a probe message,...
In this paper, we present a complete framework for celltype selection in modern high-performance low-power designs with library-based timing model. Our framework can be divided into three stages. First, the best design performance with all possible cell-types is achieved by a Minimum Clock Period Lagrangian Relaxation (Min-Clock LR) method, which extends the traditional LR approach to conquer the...
Given the significance of placement in IC physical design, extensive research studies performed over the last 50 years addressed numerous aspects of global and detailed placement. The objectives and the constraints dominant in placement have been revised many times over, and continue to evolve. Additionally, the increasing scale of placement instances affects the algorithms of choice for high-performance...
This paper deals with an extension of the Resource Constrained Project Scheduling Problem (RCPSP), which involves resource transfer delays. A flow model is used in order to formalize this extended RCPSP, which contains the standard RCPS, and leads us to introduce the Timed Flow Polyhedron and to state several structural results. This framework gives rise to a generic Insertion operator, as well as...
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