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The use of unobtrusive sensors for physiological monitoring is growing in popularity. Advantages such as their non-contact nature and their limited cognitive demand on the user can increase acceptance and usefulness in certain populations. Biomedical applications for unobtrusive pressure sensors include the analysis of bed transfer sequences and the extraction of breathing rate during long-term trend...
In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). While this technique offers great dynamic power savings mainly in array multipliers, due to their regular interconnection scheme, it misses the reduced...
Generally, setup time and hold time are very small timing parameters for a synchronous circuit. It is very hard to accurately measure them directly by a tester from a chip outside. A novel on-chip circuit is designed to assist accurately measuring the synchronous circuit's setup/hold time. Two-step digital skew adjustment, in-field self-calibration, specially designed balanced MUX cell, path-exchange...
Designing integrated electronic control units (ECU) in the automotive domain is challenging especially when legacy sub-systems are involved. Nevertheless, important design decisions have to be made at early design stages when some performance parameters of new sub-systems may not be validated yet. To account for uncertainty in the system development we use statistical modeling and discrete event simulation...
This paper focuses on parallelization of the classic static timing analysis (STA) algorithm for verifying timing characteristics of digital integrated circuits. Given ever-increasing circuit complexities, including the need to analyze circuits with billions of transistors, across potentially thousands of process corners, with accuracy tolerances down to the picosecond range, sequential execution of...
With the increasing NRE cost of advanced process technologies, reconfigurable devices receive great attention in small and medium volume IC designs. However, lower logic utilization and slower timing performance limit the efficacy of FPGA and CPLD. In this paper, we propose an efficient hybrid LUT/SOP reconfigurable design style to exploit both the advantages of LUT-cell and SOP-cell for circuit design...
The process variation of the ultra-deep submicron technology causes significant variation in the timing characteristics of flip-flops, and it can drop functional yield seriously, affecting system timing. This paper has two objectives. First, this paper investigates the sensitivities to process variation of four representative flip-flop architectures that are popularly used in digital circuit designs...
As the present day technology is shrinking towards nanometer regime, interconnect delay is more dominant compared to gate delay. Hence the calculation of interconnect delay is more crucial and plays a major role for both performance and physical design optimization for high speed CMOS integrated circuits. Many approaches primarily concentrated to find the interconnect delay rather than gate delay...
The clock frequency of a digital IC is limited by its slowest paths, designated by speedpaths. Given the extreme complexity involved in modeling modern IC technologies, often speedpath predictions provided by timing analysis tools are not correct. Therefore, several practical techniques have recently been proposed for design debugging, that combine silicon stepping of improved versions of a circuit...
The identification of speedpaths is required for post-silicon (PS) timing validation, and it is currently becoming time-consuming due to manufacturing variations. In this paper we propose a method to find a small set of representative paths that can help monitor a large pool of target paths which are more prone to fail the timing at PS stage, to reduce with the validation effort. We first introduce...
This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes...
Pulsed-latch inherits the advantage of latch in less sequencing overhead while taking the advantage of flip-flop in its convenience during timing analysis. Even though this advantage comes from the fact that pulsed-latch uses a short pulse, it is still capable of a small amount of time borrowing. A problem of allocating pulse width (out of a few predefined widths), where each width is modeled by a...
This paper presents an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using ??canary flip-flop?? that can predict timing errors. A 32-bit Kogge-Stone adder whose performance was controlled by body-biasing was fabricated in a 65 nm CMOS process. Measurement results show that the adaptive control can reduce the power dissipation by 46% in comparison...
Critical path selection plays an important role in testing of small delay defects (SDD). For some timing-balanced circuits, the numbers of candidate critical paths may be very large, and this will make Monte Carlo simulation based statistical timing analysis very inefficient. A fast path selection approach based on graph partition is proposed in this paper. First, a critical path graph (CPG) is generated...
With the challenges of growing functionality and scaling chip size, the possible performance improvements should be considered in the earlier IC design stages, which gives more freedom to the later optimization. Potential slack as an effective metric of possible performance improvements is considered in this work which, as far as we known, is the first work that maximizes the potential slack by retiming...
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will adapt random delays at runtime due to time borrowing. The central problem to determine the timing yield is to compute the probability of the presence of a positive cycle in the latest latch timing graph. Existing algorithms...
In this paper, we proposed a unified multi-corner multi-mode (MCMM) static timing analysis (STA) engine that can efficiently compute the worst-case delay of the process corners in various very large scaled circuits. Our key contributions include: (1) a seamless integration of the path-and parameter-based branch-and-bound algorithms so that the engine is very robust for different kinds of circuits,...
In this paper we propose a scheme for enhancing the timing performance of a pre-designed synchronous sequential circuit. In the proposed scheme, a circuit is driven by two clocks. One of them is the conventional clock while the other one, having a shorter period, is applied when the circuit stabilizes well before the critical delay. We use a symbolic algorithm to analyze the timing behavior of the...
With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit performance are likely to suffer the most from this phenomena. While Statistical static timing analysis (SSTA) is used extensively for this purpose, it does not account for dynamic...
Safety-critical automotive systems must fulfill hard real-time constraints for reliability and safety. This paper presents a case study for the application of an AUTOSAR-based language for timing modeling and analysis. We present and apply the Timing Augmented Description Language (TADL) and demonstrate a methodology for the development of a speed-adaptive steer-by-wire system. We examine the impact...
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