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In this poster we present an enhanced version of IEEE 802.21 Media Independent Handovers services (MIH) to optimized the network and handover performance. We added features and components in MIH architecture to enable the quick delivery of information to Mobile Nodes (MNs) to optimize the handover process. We added caches and database within Point of Access (PoA) and Media Independent Information...
Service providers are experiencing a challenge that is caused by the explosive growth in demand for high-speed connections to and across metropolitan, regional and core networks. Operators are under pressure to increase the capacity of their networks to meet these ever growing requirements. To improve service agility and network efficiency and reduce costs throughout their entire infrastructures,...
In this paper, a fast-lock analog delay-locked loop (DLL) using the dual-slope technique is presented. The architecture of the proposed DLL uses an improved charge pump and two kinds of the phase detector to achieve faster locking time, smaller area cost, and better jitter performance. The DLL was designed using a 0.35 µm standard CMOS process with a 3.3V supply voltage. The simulation results show...
In Wireless Multimedia Sensor Networks (WMSNs), data fusion and collaborative in-network processing operations often require effective multimedia synchronization control. Extensive researches have been done in the traditional networks. Most of these works assume that there exists a powerful synchronization controller in the network. However, for WMSNs, the in-network processing of the multimedia content...
As CMOS technology has scaled, supply voltage has dropped, chip power consumption has increased, and clock frequency has increased, the effects of jitter become critical and jitter budget gets tighter. Jitter can be decomposed into several components, each having specific sets of characteristics and root causes. This paper presents a short review of jitter fundamentals including a discussion of the...
This paper presented a study about design and simulation of a scenario TDi (Television Digital Interactive), consisting of a transmitter network TDT (Terrestrial Television Digital) and the return channel for interactivity IP. This present the results and their analysis regarding to: delay, jitter and packet loss on the platform, changing the transmission rate. It is a comparative analysis of various...
The most popular Differentiated Services composed of two key components: traffic conditioning and PHB (Per Hop Behavior). This paper addresses the affects of a packet handling mechanism LLQ (Low Latency Queuing) and several dropping schemes to quality of service in term of delay, jitter and packet loss. These schemes include RED (Random Early Detection), WRED (Weighted Random Early Detection) and...
With the growth of data-capable, multi-interface wireless and mobile devices, a lot of research work is being done on handover management and network selection in heterogeneous environment. The goal is that a user should be able to select an appropriate wireless network according to its service requirements and seamlessly handover to that network regardless of the underlying wireless technology being...
Regarding the necessity of internet and also increasing demand for various services, WiMAX network with high bandwidth and suitable speed of transfer can be considered as a solution for public access. This technology with production in considerable volumes from fixed to portable versions shows notable progress in wireless connectivity. Capability of Quality of Service (QoS) support provides user satisfaction...
Avionics Full DupleX Switched Ethernet (AFDX) is a promising technique that can replace the existing avionics data buses, such as ARINC429 and MIL-STD-1553B. However, when the time interval between the reception of the original frame and its duplicate copy is too large, the redundancy management strategy may fail in some worst case scenarios. In this paper, an active delay variation control algorithm,...
The IEEE 802.1 Audio Video Bridging (AVB) standard is increasingly seen as a next generation real-time communication system for various application domains. The most important requirements are a short latency and a low jitter of the data transmission. One of the biggest impacts on the latency and the jitter of a reserved real-time stream is the interfering non real-time traffic. This paper presents...
The conduction delay in neural systems has been proven to play an important role in processing neural information. In hardware spiking neural networks (SNN), emulating conduction delays consists of intercepting and buffering spikes for a certain amount of time during their transfer. The complexity of the conduction delay implementation increases with high spiking rates; it implies (1) storing a large...
Mobile broadband and Voice over IP communication improved considerably in the last years, but both technologies have been developed independently from each other. VoIP has special Quality of Service needs, among them mostly delay, jitter and packet loss could be critical in HSDPA networks. In this survey an HSDPA delay and packet loss analysis has been executed, based on VoIP traffic, using the live...
This study presents a 6-Gb/s clock and data recovery (CDR) for the high-speed data transmission systems. Similar to the concept of the oversampling CDR, the proposed CDR presents an alternative scheme, which uses the data delay window (DDW) and a sensing-amplified phase detector (SAPD) to substitute the conventional DFF-based PD. It shows that the NRZ data could be aligned and recovered by the only...
A 2 GHz to 8 GHz wide-range multi-phase distributed delay-locked loop (DDLL) has been proposed. The architecture achieves wide operating frequency range by adding a digital phase selector into the DDLL [1]. The insertion phases which are generated from digital phase selector with minor phase error could be fine-tuned by the voltage-controlled delay cells in the DDLL independently. The test chip was...
A clock-deskewing circuit (CDC) using a dual delay-locked-loop technique is presented. The CDC can synchronize the clocks for a chip-to-chip system without delay measurements and dummy delay elements. Simulated in a 0.18µm CMOS technology, the maximum operating frequency is 1.5 GHz and the cycle-to-cycle clock jitter is 7.74 ps. Total power dissipation of the CDC is 56mW under a 1.8-V supply.
This paper introduces a novel Timing Generator Format Controller (TGFC) circuit that produces programmable multi-gigahertz signals with "timing-on-the-fly" capability. For the first time (we believe), timing edges can be programmed to occur at almost any point during the test, limited only by a minimum pulse-width (~70ps) and maximum sustainable data rate (~3.2Gbps in the prototype). Timing...
A fast-lock-in harmonic-free all-digital delay-locked-loop (ADDLL) in STMicro 32nm CMOS technology is presented. The ADDLL uses a novel complementary delay line with lattice-type delay elements. The complementary line can effectively reduce at most 50% active delay elements than a single line. Less active delay elements make better suppression of supply-induced jitter. The lattice-type delay element...
Desynchronizing streams of frames through the means of offsets has today become common practice in automotive CAN networks. This is because this traffic shaping strategy is very beneficial in terms of reducing response times especially at high load levels. However, to the best of our knowledge, there is no result available in the literature that allows the response times of frames with offsets to...
The majority of research into schedulability analysis for CAN is based on the assumption that the highest priority message ready for transmission at each node on the network will be entered into arbitration on the bus. In practice; however, some CAN device drivers and communications stacks implement queuing policies that are not strictly priority-based, invalidating this assumption. In this paper,...
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