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This paper presents a 25 Gb/s clock and data recovery circuit using a full-rate clock and quadrature data phases. An adaptive slicer is used in the system front-end to equalize the distorted data to minimize duty-cycle distortion due to inter-symbol interference. The proposed structure uses an open-loop phase averaging block in the data path to generate the required quadrature phases for phase detection...
A novel parallel semi-systolic semi-scanned array architecture is proposed for the implementation of four-dimensional (4-D) IIR filters. These filters have emerging applications in computed tomography (CT), volumetric ultrasound, and light field processing for computer vision. The proposed architecture can be applied to a broad class of 4-D IIR filters, and we show results for a frequency-planar depth-selective...
This paper presents a low-power dynamic comparator utilizing a novel time-domain bulk-driven offset cancellation scheme with minimal additional power consumption and delay. It uses an open loop dynamic phase detector to achieve very high precision. The circuit is designed in a 0.6-µm process. The simulation results show that the circuit consumes 540 nA current at 100 kHz clock frequency and the proposed...
This paper presents a high efficient 13.56 MHz near field communication (NFC) transmitter in 0.18 µm CMOS process. A pulse width modulation (PWM) technique is employed to generate the ASK modulated output and to improve the transmitter efficiency. The proposed NFC transmitter can provide 0 ∼ 100% modulation depth in digital 6-bit accuracy. The multi-ASK modulation depth is realized by employing a...
A clock skew-compensation and/or duty-cycle correction circuit (CSADC) is indispensably required to maximize the performance of synchronous double edge triggered systems. Most conventional CSADCs adopted a cascade structure that inherits a lower performance property so as to slower the locking procedure, meanwhile the dual loop design results in more power consumption and design complexity. A compact...
This paper describes implementation issues for high speed 2-step-flash analog-to-digital converters (ADCs) without digital correction. A novel implementation for a multiplying digital-to-analog converter (MDAC) is described, which is a sample-and-hold amplifier, which includes a DAC, residue amplification and correlated double sampling (CDS), thereby omitting two-phase compensation differences. No...
This study presents a 6-Gb/s clock and data recovery (CDR) for the high-speed data transmission systems. Similar to the concept of the oversampling CDR, the proposed CDR presents an alternative scheme, which uses the data delay window (DDW) and a sensing-amplified phase detector (SAPD) to substitute the conventional DFF-based PD. It shows that the NRZ data could be aligned and recovered by the only...
A 2 GHz to 8 GHz wide-range multi-phase distributed delay-locked loop (DDLL) has been proposed. The architecture achieves wide operating frequency range by adding a digital phase selector into the DDLL [1]. The insertion phases which are generated from digital phase selector with minor phase error could be fine-tuned by the voltage-controlled delay cells in the DDLL independently. The test chip was...
Moving into the era of nanoscale devices, reliable clock distribution becomes a challenging problem due to the growing impact of process variations. This paper deals with this difficulty, especially on implementing useful clock skew. One possible robust way is by using programmable delay elements (PDEs) since PDEs can be adjusted after fabrication. However, with this benefit, using PDEs takes large...
A clock-deskewing circuit (CDC) using a dual delay-locked-loop technique is presented. The CDC can synchronize the clocks for a chip-to-chip system without delay measurements and dummy delay elements. Simulated in a 0.18µm CMOS technology, the maximum operating frequency is 1.5 GHz and the cycle-to-cycle clock jitter is 7.74 ps. Total power dissipation of the CDC is 56mW under a 1.8-V supply.
This paper treats post-silicon skew tuning for improving performance yield under various delay variations, and proposes a novel PDE tuning algorithm which utilizes only the result of setup and hold timing tests, not the result of delay measurements. Our algorithm is based on “trial-and-error” approach, and it has a proper level of robustness against the variation of each PDE characteristics. As far...
In this paper, a design of the first-order Frequency-based Delta-Sigma Modulator (FDSM) utilizing multi-phase quantizer is presented. The VCO (Voltage-Controlled Oscillator) which behaves as a voltage-to-phase integrator will be proposed to generate multiple output phases. Each phase output from the VCO drives a counter using the proposed CMSA-FF (Current-Mirror Sense-Amplifier Flip-Flop), producing...
With CMOS technology shrinking to nanoscale regime, the susceptibility of a single chip to soft errors increases. Hence, the critical charge (Qcrit) of circuit decreases and this decrease is expected to continue with further technology scaling. In this paper previous hardened latch circuits are analyzed and it is found that previous designs offer limited protection against soft error especially for...
Three-dimensional integrated circuits (3D-ICs) create new test challenges. Because of the limited number of test pads available in pre-bond test, the IR-drop can become a serious problem in delay test. In this paper we present a low-power delay test architecture, in which scan flip-flops are partitioned into groups that can be selected turned off in the capture cycles. As a result, power consumption...
Triple modular redundancy (TMR) is a common method to implement fault-tolerant circuits. Traditionally, TMR is realized by triplication of components. In order to reduce the area overhead of TMR another approach was proposed on coarse grained reconfigurable architectures (CGRAs). In that approach spare functional units (FUs) are used for redundant computation of results. However, it was not shown...
A time to digital converter for positron emission tomography readout circuits is presented. The converter is based on a ring oscillator and is optimized for low power consumption down to 36 µW at low event rates. Non-linearities caused by the oscillator startup are corrected in the digital domain. The proposed correction scheme is able to estimate the non-linearities of the converter without additional...
This paper introduces a novel Timing Generator Format Controller (TGFC) circuit that produces programmable multi-gigahertz signals with "timing-on-the-fly" capability. For the first time (we believe), timing edges can be programmed to occur at almost any point during the test, limited only by a minimum pulse-width (~70ps) and maximum sustainable data rate (~3.2Gbps in the prototype). Timing...
A Hierarchical Torus Network (HTN) is a 2D-torus network of multiple basic modules, in which the basic modules are 3D-torus networks that are hierarchically interconnected for higher-level networks. Three deadlock-free adaptive routing algorithms called link-selection, channel-selection, and a combination of link-selection and channel-selection was proposed for the efficient use of physical links...
This paper mainly proposes a timing scheme of a digitally controlled DC-DC converter, which is described in hardware description language (HDL) at the functional level. FPGA is adopted for the optimization of computation, sampling and modulation to get precise and fast dynamic response of DC-DC converters. The concept of this timing scheme is broad and includes DPWM scheme, sampling scheme and computation...
Parameter variations in nanometer process technology are one of the major design challenges. They cause to be increased delay on the critical path and to change the logic level of internal nodes. The basic concept to solve these problems at the circuit level, design-for-variability (DFV), is to add error handling circuits at the conventional circuits so that they are robust to nanometer related variations...
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