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In this work, we demonstrate the use of a non-traditional logic for the implementation of a dual-modulus prescaler. The proposed prescaler consumes less power than TSPC designs and is faster than ETSPC designs. The maximum speed reaches up to 96% of that of a single divide-by-2 D-flip-flop, the theoretical limit. Implemented in 130-nm CMOS technology, the maximum input frequency reaches 14.1GHz with...
In this paper, a fast-lock analog delay-locked loop (DLL) using the dual-slope technique is presented. The architecture of the proposed DLL uses an improved charge pump and two kinds of the phase detector to achieve faster locking time, smaller area cost, and better jitter performance. The DLL was designed using a 0.35 µm standard CMOS process with a 3.3V supply voltage. The simulation results show...
In recent years, many research results have discussed the mixed static-domino high-speed circuit. However, most research neglects to discuss how to implement their results. Silicon Intellectual Property plays very important roles in the design of current complex integrated circuits. In this paper, we construct a new pipeline mixed static-domino high-speed circuit synthesized methodology. The cell-based...
Network switches are typically designed for best- effort Internet traffic. Most of existing studies have been focused on improving throughput and delay performance in an average sense rather than providing guaranteed delay bound that is critical for real-time applications. It has not been fully investigated how to design an efficient packet switching algorithm for real-time applications. In this paper,...
This paper describes the architecture (circuit design) and principles of operation of sigma-delta Sigma-Delta time-to-digital converters (TDC) for high-speed I/O interface circuit test applications, they offer good accuracy with short test times. In particular, we describe multi-bit TDC architectures for fast testing. However, mismatches among delay cells in delay lines degrade the linearity...
This paper describes the current Smart high voltage substation where Merging Units and other protection devices require high-precision time synchronization, and analyzes the time synchronization significant role in the Smart substation. With the expansion of the IEC 61850 standard in Smart substation automation applying, the IEEE 1588 which can achieve sub-microsecond level of accuracy seems to be...
Current VLSI systems-on-Chips (SoCs) integrate billions of transistors and are clocked with multi-gigahertz clock frequencies. As the geometrical dimensions of both devices and wires in theses systems become smaller, the internal communication performance between the SoC's blocks is heavily affected by the on-chip interconnect wire delays. In this paper, we propose a high efficient mesochronous outfit...
Nanoscale VLSI design faces unprecedented reliability challenges in the presence of prevalent catastrophic defects, soft errors and parametric variations. We construct minimum logic networks of guaranteed single soft error resilience by combining error detection and clock gating, and leveraging an existing fault-secure logic design technique, which is to construct group-sliced logic networks with...
Process variability becomes prominent for circuits using nanometer manufacturing technology. With aggressive voltage scaling, unexpected failures occur due to excessive timing variation. Yield, number of components, and process variability are intrinsically linked. In this paper, we study the setup and hold time definition, margin, and characterization methodology. A new statistical margin quantifying...
Paths that cannot be sensitized during functional operation do not need to be optimized for speed, and their delays may be higher than the clock period. This paper uses functional broadside tests for path delay faults in order to avoid overtesting due to the detection of faults that are associated with such paths. To ensure that as many small delay defects as possible will be detected, the paper considers...
Resistive open fault (ROF) represents common manufacturing defects causing extra delays and reliability risks in affected circuits. ROF behavior is sensitive to the supply voltage and the resistance of open (RO). Modeling this fault behavior and detectability with the supply voltage helps in distinguishing between faults as well as testing of multi-voltage designs. While previous ROF models did not...
In this paper, we propose several design approaches to extend useful voltage scaling (i.e. voltage scaling with net energy savings) beyond the conventional limit, which is imposed by the rapid increase of leakage energy overhead in ultra low voltage regimes. We are able to achieve such extra voltage scaling and thus energy savings without compromising performance and variability through minimizing...
This paper proposes a temperature and process compensated clock generator using a feedback TPC (temperature and process compensation) bias circuit. With the proposed feedback TPC bias based on the OPA, MOS transistors and resistors, the BJT required in traditional bandgap bias circuit could be avoided. Thus, it is easy to be integrated with less area penalty. The proposed design is implemented using...
With ever increasing demands on spectral efficiency, complex modulation schemes are being introduced in fiber communication. However, these schemes are challenging to implement as they drastically increase the computational burden at the fiber receiver's end. We perform a feasibility study of implementing a 16-QAM112-Gbit/s decision directed equalizer on a state-of-the-art FPGA platform. An FPGA offers...
This paper describes improvements to the technique of velocity selective recording (VSR) in which multiple neural signals are matched and summed to identify excited axon populations in terms of velocity. The signals are acquired using a multi-electrode cuff (MEC) which is now available as a component for use in implantable neuroprostheses. The improvements outlined in the paper involve the replacement...
Strengthening failure mechanisms accentuate timing errors as a real threat in nanometer technology microprocessor cores. In this work, we present a low-cost and low-power, multiple timing error detection and correction technique, which is based on a new flip-flop design. This flip-flop exploits a transition detector for error detection along with an asynchronous local error correction scheme to provide...
Nature-inspired routing protocols have been subject to a great research activity. Their decentralized nature and low requirements make them highly suitable for Wireless Sensor Networks (WSN) where individual nodes operate without central control and without global overview of the network status to achieve global tasks. This paper proposes a hybrid QoS routing protocol for WSN based on a customized...
With the advent of deep sub micron era, design closure is becoming harder to achieve. In high-level synthesis, slack is a very effective means of tolerating uncertainties. Thus, several research efforts have been paid to study the slack-driven high-level synthesis problem. However, previous works cannot actually maximize the total slack value, because they are limited to either the operation scheduling...
This paper presents a 22-bit time-interpolated Time-to-Digital Converter (TDC) with 110ps temporal resolution for biochemical sensing applications, which utilize time-resolve luminescence imaging technique. The TDC achieves wide dynamic range operation by incorporating a hybrid architecture that combines a 14-bit digital counter based coarse TDC and an 8-bit Voltage-Controlled Delay Line (VCDL) based...
This paper presents a flash-type Time to Digital Converter (TDC) based on parallel delay elements in 65-nm CMOS process technology. By using parallel delay elements the conversion resolution of the TDC becomes equal to the difference of delay elements rather than the delay time of each element. A Sensed Amplifier Flip Flop (SAFF) ensures narrow sampling window. Operating at 1.2-V supply, this TDC...
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