The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Recent advances in ADCs have enabled the development of low power receivers for wireless communication applications. In this paper we will discuss a specific class of ADCs, namely sigma delta ADCs. A brief overview of challenges in the design of these ADC's will be discussed along with the recent advances and techniques in overcoming these challenges. Two specific examples in the context of narrow...
3D chip stacking technology has been gaining traction in recent years, as academia and industry are showing greater interest in going vertical. However, most research so far has been limited to theoretical analysis due to lack of industry-standard CAD tools to design 3D chips. In this paper, a 3DIC implementation of a single precision floating-point unit is discussed with the aim of identifying limitations...
Continuous-time delta sigma (CT-ΔΣ) ADCs are established as the data conversion architecture of choice for the next-generation wireless applications. Several efforts have been made to simultaneously improve the bandwidth and dynamic range of ΔΣ ADCs. We proposed using two-step quantizer in a single-loop CT-ΔΣ modulator to achieve higher conversion bandwidth. This paper presents a tutorial for employing...
Aimed to reduce the overheads using the Time Management (TM) in HLA based distributed simulations, the TM based on publish-subscribe topology information is investigated. The condition under which the message may be received before its causal predecessor is firstly analyzed. And then, the TM algorithms using vector clock are put forward, in which the condition is judged before the clock is comparing...
We studied a backside timing analysis technique utilizing Time Resolved Imaging Emission Microscopy (TRIEM) which can acquire emission data locations and timing simultaneously from an activated LSI chip. In this paper, we will present two case studies of actual failed chips. One is a delay fault case, and the other is a current fault case. Then, we will propose an analysis flow applying TRIEM based...
This paper proposes an algorithm to construct an X-clock tree with double via insertion that connects several voltage islands for power minimization. We first construct the X-clock tree for each voltage island and make double via insertion for this tree to improve yield and reliability. Then we combine these X-clock trees based on a well-defined connection with inserted level shifters to reduce power...
We demonstrate a method to compare optical clocks approaching 10−17 uncertainties through the exchange of optical pulses from phase-locked frequency combs. We discuss results over a 120 m air path and prospects for longer distances.
To securely exchange data over public networks, such as the Internet, organizations often utilize Virtual Private Networks (VPNs). However, relying on these potentially large overlay networks makes them vital targets for Denial-of-Service(DoS) attacks. Thus, recent approaches for VPN auto-configuration address DoS resistance by employing distributed management algorithms. Nevertheless, there is no...
For the design of real-time embedded systems, analysis of performance and resource utilization at an early stage is crucial to evaluate design choices. Network Calculus and its variants provide the tools to perform such analyses for distributed systems processing streams of tasks, based on a max-plus algebra. However, the underlying model employed in Network Calculus cannot capture correlations between...
This paper presents two fully synthesizable and emulation friendly delay cell designs that the authors have successfully implemented in a real emulation environment. Due to the analog nature of delay logics, none of the commercial emulators were able to support the actual delay behavior. Thus, manual additions of register were needed for each customized scenario. The effort required is huge and highly...
Today, local data networks, many last-mile access networks and even some backbone networks are based on packet transmission protocols, especially the Ethernet. Generally, there are several protocols and standards, which could be used for the purpose of clock distribution (synchronization) over packet networks. One of the most accurate protocols is Precision Clock Synchronization Protocol (PTP, IEEE...
MultiCore processor is one of the promising techniques to satisfy computing demands of the future consumer devices. However, MultiCore processor is still threatened by increasing energy consumption due to PVT (Process-Voltage-Temperature) variations. They require large design margins in the supply voltage, resulting in large energy consumption. The combination of DVS (Dynamic voltage scaling) technique...
This paper presents a programmable half-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O links. The CDR is implemented in TSMC 28nm high-k metal-gate CMOS technology and covers a continuous range of data rates from 2.5Gb/s to 12.5Gb/s. The higher data rate is achieved by demultiplexing and decimating the sampled data in order for the subsequent circuit to operate at a much...
This paper presents a soft error hardened latch suitable for reliable operation. The proposed circuit is aimed to tackle the particle hit effect on the internal nodes, external logic, as well as the pulse generator circuit. The hardening method is based on redundancy to protect internal nodes and filter out transients resulted from combinational logic. It also uses redundant clocking technique which...
Embedded memory access time is an important parameter that determines the performance of the memory. To accurately characterize the embedded memory access time across Process, Voltage and Temperature (PVT) variation is always a challenge. In order to get more accurate memory access time data across PVT, the proper implementation of embedded memory access time measurement circuitry and characterization...
In this paper, a monotonic and low-power digitally controlled oscillator (DCO) with cell-based design for System-On-Chip (SoC) applications is presented. The proposed DCO employs a cascade-stage structure to achieve high resolution and wide range at the same time. Besides, based on the proposed two-level controlled interpolation structure, the proposed DCO can provide monotonic delay with low power...
Clock gating is one of the important techniques to achieve low power and small area in high-performance synchronous circuit design. In this paper, we propose a three-phase clock gating optimization methodology by using clustering and merging algorithm to construct a gated clock tree with minimal number of clock gating cells and buffers. In addition, according to the fan-out numbers of a clock gating...
The next-generation two-way satellite time and frequency transfer (TWSTFT) is to compare clock difference at the sub-nanosecond level. However, many uncertainties, including ionospheric effects, still have to be much well studied for farther reduction. Now, there is a next-generation TWSTFT technique using dual pseudo-random noise (DPN) codes; it has high precision for clock comparison and can also...
Because of the ever increasing number of cores present on a single chip, fast and energy efficient, inter-core data communication has become a major concern. Various networkon-chip (NoC) topologies and flow controls have been presented in literature. In this paper, for the first time, the benefits of a hierarchical heterogeneous NoC are quantized using a comprehensive circuit-interconnect technology...
As the size and complexity of embedded systems are growing, the area cost and performance of the LSI circuits are becoming more crucial. A critical bottleneck for them is interconnections such as multiplexers (MUXs). Thus, a hardware synthesis technique for reducing MUXs, especially during the earlier design phase, has been demanded. This paper presents a novel MUX reduction technique in high-level...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.