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This paper investigates the failure mechanism of SiC power MOSFETs during avalanche breakdown under unclamped inductive switching (UIS) test regime. Switches deployed within motor drive applications could experience undesired avalanche breakdown events. Therefore, avalanche ruggedness is an important feature of power devices enabling snubber-less converter design and is also a desired feature in certain...
Driven by rapid growth in wireless demand, spectrum sharing has recently been the focus of extensive research. A common concern is how to address coexistence-related interference, especially when the involved systems operate under different protocols. In this paper, we outline a framework for exploiting full-duplex (FD) capabilities to support coexistence in a heterogeneous spectrum sharing environment...
Electric Vehicle (EV) has emerged as a solution for the growing concerns on pollution and depleting oil resources all over the world. The performance and efficiency of an EV mainly depends on the power electronic switching devices used in it which, in turn depends on the properties of materials used in its fabrication. Traditional semiconductor material like Silicon has been widely used for the fabrication...
One of future device candidates for the Si platform integration, the Ge pFinFET, is evaluated for two different shallow-trench-isolation (STI) processes at low temperature operation. The effective mobility around 700 cm2/Vs at 77 K is reported for both STI processes, as a result of the compressive strain in the channel. Regarding the OFF-state region, it is found that the substrate current plays an...
This paper describes a complete process/design co-optimization methodology based on Fully Depleted SOI (FDSOI) technology. A process optimization is detailed through significant effective capacitance reduction, in order to optimize jointly frequency/leakage ratio and high frequency performances. In this objective, an efficient and low cost offset-spacers morphology has been designed to achieve maximum...
In this paper, the radiation response of 90nm bulk Si MOS devices irradiated by heavy ions is experimentally studied. Due to the intrinsic random incident of heavy ions, different performance degradation is observed, such as threshold voltage shift, saturation current change and maximum transconductance degradation. These performance degradations may be attributed to the displacement damage in channel...
This paper aims at demonstrating, for the first time, the use of back bias to improve the analog performance of current mirrors composed by self-cascode structures with 25 nm-long n- and p-type UTBB SOI MOSFETs. The use of back gate bias has shown to enhance the intrinsic gain of p-type devices by about 7 dB, making it higher than the one from a single device with equivalent channel length whereas...
Nowadays, electronic circuits based on wide range of organic materials with semiconductor properties are still perceived as a somewhat unconventional design approach and fabrication technology. However, it could potentially deliver many significant advantages. Materials for organic electronics are typically lighter, flexible, easier to handle and less expensive in comparison with traditional inorganic...
The power MOSFET wafers which base on silicon substrates are almost reaching end of road, lacking on both performance and cost. It was widely predicted in the industry that next generation wafers should come from Gallium Nitride (GaN) substrate. This new material is expected to be the dominant technology due to its competitive in almost all aspects. Many high power device providers are making deep...
This paper will examine challenges in future device scaling and the implications arising from difficulties in delivering scaling benefits from devices to the circuit level, and ultimately up to the system level. These implications will serve to highlight opportunities in design-technology interactions to aid in overall system scaling.
The feasibility of medium-high fraction SiGe based FinFET pMOS devices for a sub-10nm CMOS logic technology from a performance (IEFF @ fixed IOFF) standpoint is evaluated, considering three key device aspects — stress, band-to-band-tunneling (BTBT), and interface charge density (DIT). The analysis reveals that while for high Ge (>90%), performance is limited by BTBT, overall stress reduction beyond...
A detailed statistical characterization of drain current local and global variability in sub 15nm gate length Si/SiGe Trigate NW pMOSFETs is carried out. An analytical mismatch model is used to extract the main matching parameters. Our results indicate that, despite their very aggressive dimensions, such devices maintain relatively good variability performance.
Well-calibrated predictive TCAD simulations are employed to generate target data for compact models for better pre-V1.0 PDK development. A reliable re-centering technology has been developed which can accurately migrate the global and local variability and the corresponding corners. FinFETs calibrated to published data by Intel at the 14nm technology node are employed as test-bed devices.
We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first approach, with Ge-enrichment performed prior to the STI module and the SiGe-last approach using only a SiGe epitaxy after the STI module. We evidence reduced layout effects in the SiGe-last integration featuring Si/SiGe bilayer. SiGe-last shows...
Interest in resorbable and biodegradable materials originates from their potential in food packaging, environmental science and ecology, but also in medicine and biotechnology. Till very recently, electronics has not been on such development paths. However, recent advancements in material science, thin processing and nanotechnology offer the prospective of high performance electronic devices which...
This paper will examine challenges in future device scaling and the implications arising from difficulties in delivering scaling benefits from devices to the circuit level, and ultimately up to the system level. These implications will serve to highlight opportunities in design-technology interactions to aid in overall system scaling.
In the present work we will show our complementary TFET technology, which allows for the co-planar integration of InAs/Si p-TFETs and InAs/GaSb n-TFETs. We demonstrate both types of devices, show the results of the electrical characterization at room temperature and down to 125K. The p-TFETs exhibit excellent performance with Ion of a couple of µA/µm (|VGS| = |VDS| = 0.5V) combined with average subthreshold...
Reconfigurable field effect transistors (RFETs) are attractive for analog applications exploiting their inherent switch-ability from n-type to p-type behavior. Simulation studies by means of an experimentally calibrated 3D numerical device simulator reveal that the recently proposed simplified single gate (SG) RFET architecture leads to a two times larger intrinsic transit frequency while providing...
In this paper, a design of Double gate junctionless MOSFET using Germanium for improvement of performance parameters is proposed. As Germanium is having higher mobility of electrons than the Silicon, it suitable for the smaller semiconductor devices with more drain current ratio than Silicon with high throughput. Furthermore, performance of Germanium DGJLT is evaluated with different high-k dielectric...
The effects of very high ion flux and very large ion beam current need to be investigated if very high ion flux is to be considered as a method of throughput increase for high-current ion implantation. In this work, Synopsys TCAD Sentaurus was used to simulate As ion implantation in order to obtain silicon amorphization and dopant distribution data. The TEM images are consistent with TCAD simulation...
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