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X-ray fluorescence analyze, the milliohm meter and X-ray energy dispersive spectrometer were used to investigate the impurities and electric resistance of the copper wire. By the polishing and corrosion testing, the different grain sizes were observed by scanning electron microscopy. The impurities can effect on the hardness and electrical conductivity of the copper wire. The grain size also affects...
Induction motors operating in industries consume a significant part of total energy produced in any developing or developed nation, and studies have shown that approximately 40% of Induction motors are oversized or under loaded. Oversizing leads to a decrease in operating efficiency & performance of the motor, and hence there is an opportunity for energy saving. Considering this fact, this paper...
In this study, a nanowire crossbar Si3N4/SiO2 bi-layer resistive random access memory (ReRAM) with copper (Cu) electrode has been fabricated successfully by a Cu chemical displacement technique (Cu-CDT). The Cu-CDT could overcome the difficulties of Cu dry etching and achieve a high density crossbar array of Cu-based ReRAM. Compared with other Cu deposition techniques, Cu-CDT exhibits several advantages...
Graphene is a wonderful material with outstanding properties which is ideal for micro-electro-mechanical systems (MEMS) and also nano-electro-mechanical systems (NEMS) like sensors and switches including strain gauges, mass and force sensors. Graphene is single atom thick layer of graphite which consists of carbon atoms that are bonded together in a hexagonal honeycomb lattice. A way of fabricating...
This paper reports direct in-situ stress measurements with microscale spatial resolution in glass using Raman spectroscopy. This new technique is used to assess the reliability of copper-plated laser-drilled through package vias (TPV) in ultra-thin bare glass interposers. Bare glass panels of 3"x3" size, with 137µm and 237µm thicknesses were fabricated with laser-drilled through-package...
Open through silicon vias are direct vertical connections between different integration levels of a chip which provide higher performances per unit area in three-dimensional integrated circuits. The reliability of such structures in integrated circuits constitutes an important issue in microelectronics. This paper deals with electromigration reliability and lifetime evaluation of open copper through...
In this paper, anodic aluminum oxide (AAO) is introduced as a potential new material for making interposers, and a low cost process for building high density interposers is demonstrated. Hard anodic process was used to create thick anodic aluminum oxide (AAO) films containing high density vertical nanopores on aluminum substrates. Silicon dioxide (SiO2) deposition by plasma enhanced chemical vapor...
For ultra-fine pitch and high density Cu pillar low temperature bonding (200°C), the surface contact between substrate and Cu pillar array is the key. Therefore, the fabrication quality of copper bump array affects severely the bonding results. The qualitative factors include (1) Cu pillar array height uniformity, (2) free of copper oxide layer, (3) Cu material property (e.g. elastic modulus, grain...
An ultra-thinning down to 2.6-um using 300-mm 2Gb DRAM wafer has been developed. Effects of Si thickness and Cu contamination at wafer backside in terms of DRAM yield and retention characteristics are described. Total thickness variation (TTV) after thinning was below 1.9-um within 300-mm wafer. A degradation of retention characteristics occurred after thinning down to 2.6-um while no degradation...
Direct Cu-Cu bonding has been pursued by the semiconductor industry as the next interconnection node, for its superior power-handling capability, thermal stability and reliability as compared to traditional solders. However, manufacturability of Cu interconnections has so far been severely limited by the relatively high modulus of Cu, requiring costly planarization processes to address non-coplanarities...
This paper describes the improvement of advanced semi-additive processes (SAP) to demonstrate 1.5-5 µm lines and spaces with 4-5 µm diameter photo-vias for multiple re-distribution layers (RDL) at 20 µm bump pitch on glass interposers. High performance computing systems for networking and graphics are driving ultra-high bandwidth interconnections between logic and memory devices. This signal bandwidth...
This paper demonstrates silicon-integrated, thinfilm, high-density tantalum capacitors for integrated power modules. The capacitors in form-factors of less than 75µm showed stable capacitance densities of more than 0.3 µF/mm2 with leakage of less than 0.1 µA/µF at 3 V. To the best of authors' knowledge, this is the highest capacitance density reported till date at the mentioned form-factors. Furthermore,...
The processes key to enabling 3D manufacturing, namely, bond, backgrind, and through silicon via (TSV) reveal, are extended for 300 mm glass substrates to fabricate a heterogeneous, multi-die, 2.5D glass interposer. Based on an existing silicon interposer offering, the glass interposer is comprised of multi-level "device" side copper wiring, with line space (L/S) of = 2.5 µm, built using...
The requirement of IC packages with fine line features has increased significantly. Semi-Additive Process (SAP) is the traditional way to make copper trace in the organic substrate. However, inadequate adhesion of fine line to dielectric materials occurred in manufacturing for line/space less than 5/5µm. Line embedded (LE) is another way to form fine circuitry. LE technology has several advantages...
In system level electromigration test of 2.5D IC, Joule heating enhanced electromigration failure has been found to occur in redistribution layer in the interposer. In our test samples, there are two redistribution layers (RDL), each between every two levels of solder joints, so there are three levels of solder joints. First, the microbumps connect a Si chip on top and an interposer chip in the middle...
A semiconductor industry has been encountered a memory bandwidth bottleneck toward a high density and high bandwidth system. In order to overcome those limitations, a 3D stacked high bandwidth memory (HBM) based on a through silicon via (TSV) and fine pitch interposer technology is lately introduced. By adopting this structure, thousands numbers of input/output (I/O) channels with a fine pitch can...
Current TSV integration schemes include via-first, via-middle and via-last process flows. In this paper, a low thermal budget, 10ìm pitch and aspect ratio 10 (5ìm diameter, 50ìm depth) via-last TSV module is presented. The proposed via-last module is plugged in after the thinning module, with 50ìm thinned device wafers temporary bonded to a Si carrier, using Brewer Science Zonebond® material. After...
Etch is one of the most critical processes for high-aspect ratio TSV as it defines the profile and wafer level depth uniformity of TSV, thus having a great impact on other downstream processes in TSV module and TSV backside reveal. This paper presents the challenges encountered in developing the 6μm × 55μm TSV (6μm diameter × 55μm depth) with a number of continuous process optimizations. These include...
This paper proposes a combination of annular copper and cylindrical copper as the TSV conductor to decrease the effect of thermal mismatch between copper and silicon in MEMS packaging, which results in a reliability risk between redistribution layer (RDL) and TSV. There are three important factors which may have the most serious influence on the reliability being simulated and analyzed. They are the...
The purpose of this study is to evaluate the strength of TSV silicon chips using a point-load on elastic foundation (PoEF) test, associated with an acoustic emission (AE) method for detecting local material cracks or delamination occurring during the test before the chip breaking (or catastrophic failure). The results indicate that there are no larger-than-25 dB AE signals and no via cracks occurring...
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