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An automatic, defect-oriented method is proposed for activating latent defects in analog and mixed-signal integrated circuits. Based on the topology modification technique, added stress transistors generate voltage stress that activates these latent defects. This contrasts with burn-in testing which uses increased temperatures as a fault activation mechanism. Moreover, this Design-for-Testability...
The purpose of this study was to provide a low cost manufacturing solution for Silicon Trench based Schottky rectifiers utilizing NiPt alloy composition that produces multiple barrier heights and provide designers the option to easily adjust the barrier height (BH) for rectifier designs. Higher temperatures needed to obtain larger barrier heights are generally unfavorable for trench-based Schottky...
The objective of this work is to investigate gate oxide degradation in Lateral Double Diffused metal-oxide semiconductor (LDMOS) devices associated with Polysilicon Buffered Locos (PBL) isolation. It was found that the defects in the silicon at the edge of Polysilicon Buffered Locos resulting in severe degradation of charge-to-breakdown (Qbd) occurring at the edge of the active area silicon have been...
This paper describes the development of work function measurements using Kelvin probe force microscopy (KPFM) on semiconductor materials including high-κ/metal gate layers. We show how the choice of substrate and/or underlying films affects work function quantification. Other influences on work function measurement such as sample aging, humidity, and measurement mode were also studied. Finally, TiAl...
The impact of gate voltage differences on the performance of the novel n-type silicon homojunction SOI-Tunnel FET is studied. Based on numerical simulation results using Synopsys Technology Computer-Aided Design (TCAD), the higher on-current and the ultra-low off-current are observed as compared to that of a conventional SOI-Tunnel FET. The analysis of energy band corroborates that gate voltage differences...
Deeply understanding how FinFET transistors behave causes a lot of interest and attentions. Mostly, the current, IDS, flows through the strongly-inversed layer about hundreds of angstroms in the channel of an enhancement-mode MOSFET device as a bias exceeding the threshold voltage is applied to Gate. As for FinFET devices, there are two features that are intriguing. For one thing, the leakage current...
This paper describes a half-semester module in an Introduction to Engineering course that uses microelectronics technology to introduce students to basic ECE concepts and engineering design. The module uses CMOS integrated circuit technology as a vehicle for introducing basic concepts including voltage, current, and logic levels while also providing students with perspective on how integrated circuits...
Two unique gate oxide failure mechanisms are associated with deep trench processes for a 0.18 μm power semiconductor device. One failure mode is a “mini-LOCOS” defect, that is due to inadvertent oxidation of Si in the active area during deep trench oxidation. The other failure mode is due to slip associated with dislocations from the deep trenches. These defects are eliminated by optimizing the SiN...
This paper describes the development of work function measurements using Kelvin probe force microscopy (KPFM) on semiconductor materials including high-κ/metal gate layers. We show how the choice of substrate and/or underlying films affects work function quantification. Other influences on work function measurement such as sample aging, humidity, and measurement mode were also studied. Finally, TiAl...
The purpose of this study was to provide a low cost manufacturing solution for Silicon Trench based Schottky rectifiers utilizing NiPt alloy composition that produces multiple barrier heights and provide designers the option to easily adjust the barrier height (BH) for rectifier designs. Higher temperatures needed to obtain larger barrier heights are generally unfavorable for trench-based Schottky...
An overview of three-dimensional integrated circuits (3D ICs) is presented in this paper. The key potential applications of 3D ICs that have the most impact in terms of performance, power and area are highlighted, followed by a brief overview of the different technology approaches to implement 3D ICs. Further, the key challenges to 3D integration are discussed here.
Precise Vg-pulse response of low-voltage FeFETs were systematically investigated for the first time. The FeFETs showed good reproducibility of the Vth values controlled by voltage height, time width, and number of the imposed Vg pulses. Parameter extractions of the static and dynamic ferroelectric characteristics are valuable for modeling the FeFETs and simulating the analog circuits. 10^9 cycle endurance...
We demonstrate for the first time a 20% [Ge] SiGe Macaroni channel in 3D NAND. Two alternative integration routes have been explored and High Pressure Annealing Process in D2 ambient has been applied to improve the channel and the channel-SiO2 interface. Electrical performance indicates that SiGe can improve channel conduction, with minimal impact on memory performance, but has intrinsically worse...
One of the major challenge with CMOS circuits with 22nm technology & beyond is to buried the issues of increasing in power dissipation of the circuits due to higher order effects & leakage current. The traditional transistor or MOSFET require significant amount of power so the circuit present on the chip will require a large amount of power due to presence of many transistors in the circuit...
The paper describes, the structural and temperature analysis of 4H-SiC DMOSFET (Double-implanted metal-oxide-semiconductor field-effect-transistor). The SiC based DMOSFETs are most preferred switching devices for high power conversion because of its high carrier mobility and low dopant ionization energy. The current flow is in vertical direction i.e from source in the top to the drain in the bottom,...
Unusual peaks in the transconductance gm(VGS) characteristics of n-channel UTBOX devices have been evidenced at 10 K and 77 K operation for an applied front gate voltage around 1.1 V while the back gate is grounded. The origin of this behavior was also addressed using additional low frequency noise (LFN) measurements. It is believed that the unusual peak may be related to a tunneling effect through...
In this paper a compact model for intrinsic capacitances for Tunnel field-effect transistors (TFETs) is presented. The model is derived from the carrier concentration and current flowing the channel of a Si Double-Gate (DG) n-type TFET. It represents a particularly good estimation of TFET capacitances and the flexibility of this model makes it possible to apply it for single-gate or p-type TFETs as...
In this work we present a simulation study of Si80Ge20 and Silicon vertically stacked lateral nanowires transistors (NWTs) with potential application at 5nm CMOS technology node. Our simulation approach is based on careful selection of simulations techniques in order to capture the complexity of such ultra-scaled devices. We have used ensemble Monte Carlo (MC) simulations to accurately predict the...
A method for fabrication of VeSFETs, three-dimensional fin-type MOS transistors is presented. The VeSTIC process was developed and experimentally implemented in ITE. The test devics were manufactured, and their electrical characteristics were measured. Methods for extraction of a set of the VeSFET physical parameters are proposed based on the device compact model. The flat-band voltage, mobility and...
In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. It is shown that the device achieves Ion/Ioff ratio of 5×104 considering Ion (Von= VIoff−0.5V) = 0.8×10−8 µA/µm and an average SS of 55mV/dec over two orders of magnitude of Id. Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency...
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