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In this work, we present the high frequency extraction of electrical material properties of silicon substrates. Two methods, including the substrate integrated waveguide (SIW) based method and the planar resonator based method, are used and their consistency will be shown. For the SIW-based method, a line difference algorithm is applied for the calculation of a broadband material property with the...
In this paper, the discolor on back-side revealing through-silicon-via (TSV) after wafer thinning and silicon recess process was investigated with various surface analysis methods. According to the analysis results, surface discolor could be raised by Cu oxidation during Si recess process. To eliminate the discolor occurrence, a remedy with in-situ Ar-ion bombardment was proposed which plays a role...
In this paper, the impact of microfluidic cooling on the electrical characteristics of through-silicon vias (TSVs) is investigated for three-dimensional (3-D) integrated circuits (ICs). The design and fabrication of a testbed containing TSVs are presented for two types of heat sinks (micropin-fin and microchannel heat sinks) immersed in deionized (DI) water. The high-frequency characterization of...
This paper presents one of the first comprehensive studies comparing the electrical performance of through-silicon-vias (TSVs) in silicon with through-package-vias (TPVs) in glass, considering electromagnetic field distributions, 50 ohm impedance design, and the effect of via taper. First, the electric and magnetic field distributions were analyzed using a 3D EM solver (CST Microwave Studio) for the...
Thermal management is a key challenge for TSV (through-silicon-via) enabled integrated three-dimensional microsystem and integrated microchannel cooling is believed as a promising technology because of high inner-chip cooling efficiency. In this paper, a compatible process is presented for integrating microchannel into TSV interposer and three typical types of integrated microchannel are implemented...
Deep Reactive Ion Etch (DRIE) processes used to form Through Silicon Vias (TSVs) achieve high aspect ratios by depositing polymer on the vertical sidewalls of the features. This polymer material must be removed before other materials (including dielectric liner, Cu barrier, and Cu) are deposited in the TSVs. Clean processes adapted from Cu damascene integration flows use a combination of oxygen ash...
This paper presents a new test protocol aimed at accurately determining the temperature of 3D electronic circuits as well as their heat distribution. It is based on AC electrical measurements coupled with InfraRed Lock-In Thermography (IR LIT) measurements. The circuit temperature is assessed thanks to AC resistance measurements and the Temperature Coefficient of Resistance (TCR) of metallic layers...
3D WLCSP using via last TSV (through silicon via) technology is an ideal packaging technology to meet small-form-factor, high I/O density, high-speed and most important, lower cost. For thin 3D WLCSP with TSVs, a number of critical processes need to be developed such as oxide etch, via cleaning and wafer de-bonding. In the present paper, processes for 8 inch, thin WLCSP with TSV diameter of 40µm and...
The processes key to enabling 3D manufacturing, namely, bond, backgrind, and through silicon via (TSV) reveal, are extended for 300 mm glass substrates to fabricate a heterogeneous, multi-die, 2.5D glass interposer. Based on an existing silicon interposer offering, the glass interposer is comprised of multi-level "device" side copper wiring, with line space (L/S) of = 2.5 µm, built using...
MEMS devices are continuous evolving to achieve smaller size and lower cost with improved performance. The Through silicon via (TSV) technology offers a promising approach from the perspective of MEMS device packaging and integration. In this paper, we report our latest progress on wafer level packaging of MEMS devices by via-last process. The 200mm MEMS wafer was bonded with a glass cap wafer. Then,...
We improved a through-silicon via (TSV) revealprocess comprising direct Si/Cu grinding (simultaneousgrinding of Si and Cu) and residual metal removal. In thisimproved process, direct Si/Cu grinding was performed byusing a novel grinding wheel (vitrified-bond type) and cleaningthe wheel with a high-pressure micro jet. Instead of electrolessNi-B plating, electroless Sn plating was then performed tocover...
Through Silicon Via (TSV) was original proposed for the three-dimensional (3D) IC packaging and now is realized in the high band width DRAM (HBM) application. TSV is also utilized in a passive silicon interposer and the insertion of such interposer into a flip chip packaging created another packaging platform commonly known as 2.5DIC for high density multiple ICs integration. However, since the 1st...
Warpage control is a key process character for 2.5D IC without Through-Silicon Vias (TSV). For low cost package trend, TSV is not used for advanced 2.5D IC package. Yield is still an issue for 2.5D IC package, Die-Bonding (DB) last process is applied to make sure top die is bonded on good interposer. Therefore, no top die will be sacrificed for low interposer process yield, cost could be more reduced...
Effect of thermo-mechanical stress (TMS) originating from CuSn micro-bumps (µ-bumps) and Cu through-Si-vias (TSVs) on the retention characteristics of 20-µm-thick, vertically stacked dynamic random access memory (DRAM) chip has been investigated. At cumulative probability of 50 %, the retention period decreased nearly 47% for the DRAM chip having thickness value of 20 µm as compared to the retention...
In this paper, we show that using the relation between the inductance matrix and the capacitance matrix in a homogeneous medium to extract the coupling capacitance in a through silicon via (TSV) array is inaccurate. This is because this relation assumes a lossless, homogeneous surrounding medium. We show that this model can cause an error up to 70% in coupling capacitance compared to Q3D extractor...
This paper presents a 3D circuit model capable of rapidly and accurately evaluating substrate noise coupling in the context of 3D integration. Since TSVs are large and noisy structures, the evaluation of electromagnetic coupling to and from TSVs has become crucial to the design of threedimensional integrated circuits. In this work, we present a fast and accurate 3D circuit model to this end. The model...
Conventional IC packaging requires chips to be packaged at the same level, while newly developed 2.5D/3D IC packaging utilizes skyscraper approach to stack various types of chips with diverse functions occupying similar footprint, not only reducing overall package dimension, but also improving electrical interconnection performance. The major difference between 2.5D/3D IC lies in the implementation...
This paper focuses on the thermo-mechanical reliability of a 3D-TSV MEMS in which cap layer and MEMS micro-structure layer is vertically interconnected and bonded by TSVs/micro-bumps and a sear ring. Geometrical parameters of the TSV structure and the seal ring are optimized first before the global model simulation. Smaller thickness of bottom TSV Cu and smaller opening size of silicon oxide layer...
In this paper, a novel Si interposer for hermetical MEMS oriented System-in-Package application is presented and it is a low stress, scalable platform with a stress releasing function. It's composed of Si posts which are Air-gapped from Si interposer substituting traditional Copper TSVs to function as electrical interconnection paths, re-distribution layer (RDL) and landing pads for chip stacking...
The continual downscaling of CMOS transistors, as predicted by Moore's Law, has faced tremendous challenges in terms of performance and cost reduction. Through Silicon Via (TSV) technology provides an alternative "More than Moore" solution for system level integration, resulting in smaller form factor, reduced power consumption and large bandwidth for higher data transfer rate. Via-last...
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