The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Network-on-Chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in nanoscale technologies. Application specific SoC design offers the opportunity for incorporating custom NoC architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. The aim is to generate a custom NoC that maximizes...
In this paper, we present a novel approach in Networks-on-Chip topology optimization, by considering the network power consumption, packet transmission delay, and system reliability, simultaneously. We use the Particle Swarm Optimization technique to acquire the most suitable topology architecture, which achieves maximum reliability as well as minimum delay and power consumption. The optimization...
Power characteristics of different Network on Chip (NoC) topologies are developed. Among different NoC topologies, the Butterfly Fat Tree (BFT) dissipates the minimum power. With the advance in technology, the relative power consumption of the interconnects and the associate repeaters of the BFT decreases as compared to the power consumption of the network switches. The power dissipation of interswitch...
Hardware implementation of Artificial Neural Network (ANN) is proposed by using Networks on Chip (NoC) with 5-port 2-virtual channels router, aiming at higher performance and low latency. Experimental results by NIRGAM NoC simulator show that this proposed system has higher Connection-Per-Second (CPS), higher Connection-Per-Second-Per-Weight (CP-SPW), lower communication load. Furthermore this NoC...
In Multicore Network-on-Chip, it is preferable to realize distributed but shared memory (DSM) in order to reuse the huge amount of legacy code and easy programming. Within DSM systems, memory consistency is a critical issue since it affects not only performance but also the correctness of programs. In this paper, we investigate the scalability of the weak consistency model, which may be implemented...
Photonic interconnection networks have recently been proposed as a replacement to conventional electronic network-on-chip solutions in delivering the ever increasing communication requirements of future chip multiprocessors. While photonics offers superior bandwidth density, lower latencies, and improvements in energy efficiency over electronics, the photonic network designs that can leverage these...
Traditional metallic interconnects has become the bottleneck of NoC (Network on Chip) performance due to the limited bandwidth, long delay, high power consumption and crosstalk noise. Optical Network-on-Chip (ONoC) can decrease interconnect delays and provide higher bandwidth, lower power consumption. So ONoC is believed to be a promising solution. ONoC is based on silicon-based waveguides and CMOS-compatible...
To bridge the widening gap between computation requirements of terascale application and communication efficiency faced by gigascale multi-processor system-on-chip devices, a new on-chip communication system, dubbed Wireless Network-on-Chip (WNoC), has been proposed. This work centers on the design of a high-efficient, low-cost, deadlock-free routing scheme for domain-specific irregular mesh WNoCs...
Chip MultiProcessor (CMP) architectures are dominant trend in parallel processing systems. With the number of on-chip processors rising to the hundreds, allocation and management of the processors are also important factor to achieve high efficiency of CMPs. In this paper, the authors study a Processor Allocator (PA) for CMP based on torus Network-on-Chip. The best, IFF and IAS algorithms for mesh-based...
Networks-on-chip (NoCs) have emerged as an alternative to ad-hoc wiring or bus-based global interconnection in Systems-on-Chip (SoCs). The architecture of network significantly determines system performance. This paper proposes a network on chip architecture with 2-demention mesh topology, odd-even routing algorithm, wormhole switching technique and only input buffers. The size of packet is 20 bytes...
In this paper, a methodology based on the cost of bus throughput, transmission latency and power consumption is proposed to achieve integrated optimization of NoC topology modeling and generation. The optimized framework's static and dynamic properties ensure efficient core-to-core communication of the complete network. Our approach 1) fully exploits the regularity of standard topology and the flexibility...
The paper investigates an impact of direct and combining collective communications models that may be critical for performance of parallel applications. Analysis provided for any given start-up time and message transfer time reveals the fastest collective communication mode in relation to the number of processing elements in 2D meshes and fat tree networks on a chip.
Shrinking transistor sizes and recent trends toward many-core chips have heightened the need for an efficient on-chip communication network to integrate various cores. However, buses and point-to-point interconnection will not result in scalability, modularity, and explicit parallelism, as well as may suffer great performance bottleneck. While state-of-art packet-switched network increases the communication...
Networks-on-Chip (NoCs) have been proposed as an efficient solution to the complex communications on System-on-chip (SoCs). The design flow of network-on-chip (NoCs) include several key issues, and one of them is the decision of where cores have to be topologically mapped. This thesis proposes a new approach to the topological mapping strategy for NoCs. Concretely, we propose a new topological mapping...
The increasing complexity of modern digital devices demands for ever increasing communication requirements, and for an ever increasing heterogeneity of the target applications. Specifically, different communication domains may be implemented using the same chip area, for instance to allow multiple parallel applications to be loaded onto the device. A flexible, reliable yet performant communication...
Network on Chip (NoC) is a research field path that primarily addresses the global communication in System on Chip (SoC).The selected topology of the components interconnects plays a prime role in the performance of NoC architecture, for NoC conception, high-level synthesis approaches are utilized thus the behaviorally description of the system is refined into an accurate register-transfer-level (RTL)...
This paper proposes a novel Network-on-Chip (NoC) architecture that not only enhances network transmission performance while maintaining implementation cost feasible, but also provides a power-efficient solution for interconnection network scenarios. Diagonally-linked mesh (DMesh) NoC that uses wormhole packet switching technique implements a high-performance NoC platform to meet both cost and power...
Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, many-core chips demand new interconnection strategies, since traditional crossbars or buses, common for current multi-core processors, have problems related to wires and scalability. For this reason, Networks-on-Chip (NoCs) have been developed in order to support the performance and parallelism...
As CMOS technology scales down into the deep submicron (DSM) domain, devices and interconnects are subject to new types of malfunctions and failures that are harder to predict and avoid with the current system-on-chip (SoC) design methodologies. We propose a combination of a topology and Multi-path routing which can increase fault-Tolerant and Communication load which is suitable for multimedia applications...
Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor System-on-Chip architectures. Synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.