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Network-on-Chip (NoC) has been proposed as a paradigm for the network, wireless and multimedia applications executing on embedded chips with massive data processing. It requires high speed data transferring and low power consumption, and then efficient and accurate performance estimation tools are needed for system level optimization and analysis in a flexible way. In this paper, a new NoC simulator...
With increasing scale of Network-on-Chips (NoCs), the power caused by long line wires between cores counts for a significant proportion of the NoCs energy consumption. Most of the study on NoCs topologies assume that interconnect wires between cores are same length and are short lines. Taking 2D 4×4 torus network as an example in this paper, we present a long line interconnects network model for analyzing...
With the amount of calculation for wireless and multi-media applications increasing, the Multi-Processor System-on-a-Chip (MPSoC) based on Network-on-Chip (NoC) is used to process massive data in a distributed fashion. Compared with heterogeneous architecture for general embedded low power DSP, homogeneous NoC architecture is much more flexible for dynamical task assignment. In this paper, a new NoC...
Three-Dimensional (3D) integration will take the next stage VLSI technology instead of 2D technology. In 3D chip, the electrical performances are much better than in 2D chip, for its short length. In this paper, an accurate energy consumption model of 3D Through-Silicon-Via (TSV) is proposed for power estimation of 3D Network- on-Chip (NoC). The capacitance model of isolated TSV is analyzed in detail,...
In this paper, a methodology based on the cost of bus throughput, transmission latency and power consumption is proposed to achieve integrated optimization of NoC topology modeling and generation. The optimized framework's static and dynamic properties ensure efficient core-to-core communication of the complete network. Our approach 1) fully exploits the regularity of standard topology and the flexibility...
Shrinking transistor sizes and recent trends toward many-core chips have heightened the need for an efficient on-chip communication network to integrate various cores. However, buses and point-to-point interconnection will not result in scalability, modularity, and explicit parallelism, as well as may suffer great performance bottleneck. While state-of-art packet-switched network increases the communication...
In this paper, we present a methodology for modeling, analysis and generation of NoC topology. Specially, our optimization framework of static and dynamic properties ensures core-to-core communication of the complete network. Our approach (1) fully exploits the regularity of standard topology and the flexibility of application-specific topology (2) generates a scalable network containing heterogeneous...
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