The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Long-range wireless shortcuts in Network-on-Chip (NoC) architectures are shown to significantly improve energy-efficiency in on-chip data transfer. However, over-utilization of the wireless shortcuts and non-uniform traffic patterns may result in thermal hotpots in the NoC links or switches. In this work we propose a cross-layer approach of optimizing the NoC topology to achieve a balanced traffic...
As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor densities on chips dramatically increase. While nanometer feature sizes allow denser chip designs in each technology generation, fabricated ICs become more susceptible to wear-outs, causing operation failure. Even a single link failure within an on-chip fabric can halt communication between application blocks,...
The major bottleneck in simulation of large-scale neural networks is the communication problem due to one-to-many neuron connectivity. Network-on-Chip concept has been proposed to address the problem. This work explores the drawback that is introduced by interconnection networks - a delay jitter. The preliminary experiment is held in the spiking neural network simulator introducing variable communicational...
With burgeoning growth of mobile systems, multiprocessor System-on-Chip (MPSoC) connected via Network-on-Chip (NoC) has become ubiquitous. A typical MPSoC in mobile applications consists of multiple CPU cores of varying capabilities, GPU cores, DSP cores, and crypto accelerators and such cores differ widely in their physical size and their bandwidth requirements. Traditional mesh based NoC systems...
This paper presents a fault tolerant reconfigurable Network-on-Chip (NoC) architecture using router redundancy. In case of occurrence of fault in the active router, the spare router takes its place thus the system operates normally. This scheme is topology independent, so any topology with defined routing algorithm is suitable for implementation. The system has been compared in terms of reliability,...
Network-on-chip (NoC) is emerging as an effective architecture which address the shortcomings of traditional bus-based System-on-chip (SoC). Since its better properties, such as the lower power consumption, smaller size and higher scalability, mesh is often regarded as an effective topology for NoC design. In this paper, we propose a double-layer sparse honeycomb topology as a terrific design option...
Parallelized kernels for operations research belong to the class of the diffused computations of Dijkstra and Scholten. They communicate through small, constant-length (or at least bounded length) messages and quickly reach congestion. FPGAs allow the creation of many-cores architectures and, because they are reconfigurable, can embed networks-on-a-chip (NoCs) that have been finely tuned for these...
Chip MultiProcessors (CMPs) will have dark silicon or frequently deactivated areas in a chip, as technology continues to scale down, due to power dissipation. In this work we estimate the influences of deactivated cores on performance of network-on-chips (NoCs). Even when a chip has a two-dimensional mesh topology, a deactivated core that includes an on-chip router makes topology irregular. We thus...
Adopting high-degree topologies is a promising way to reduce end-to-end latency in a network-on-chip (NoC). However, some high-degree topologies are not used in practice due to their complex layout on a chip. In this work we explore the way to systematically obtain the quasi-optimal mapping of those topologies onto a chip by modelizing the mapping problem as a quadratic assignment problem. Results...
Network-on-chip (NoC) has been introduced as a promising on-chip communication architecture to support many IP (intellectual property) cores on a single chip. Application mapping of IP cores onto a NoC topology is considered as a NP-hard problem. The increasing number of IP cores makes NoC application mapping more challenging to obtain optimum core-to-topology mapping. This paper proposes a genetic...
The continuous improving of semiconductor technology integrates more processors into a single chip. While integrate multiple processors into a chip, the interconnection network of among the cores become a dominant performance bottleneck. Accordingly, this paper provides a new on-chip interconnection network, called Self Similar Cubic (SSC), for many-core architectures. By cooperating with proposed...
The partially adaptive routing plays an important role in the performance of Network-on-Chip (NoC). It uses information of the network to select a better path to deliver a packet. However, it may have imbalanced path diversity in different directions, which makes their tolerances of traffic load differ a lot from each other. This characteristic would cause problems in traffic balancing but give us...
Networks-on-Chip (NoC) with low-radix switches forming a simple and planar topology is typically accepted as the right interconnection infrastructure for current Chip Multi Processor and high-end Multi Processor System-on-Chip. This is mainly due to its simplicity in the physical mapping on the chip. However, as the network diameter increases, latency and power consumption are increased due to the...
Recent studies have shown that to improve the performance of specific System-on-Chip (SoC) application domain, the OCI (On-Chip Interconnect) architecture must be customized, at design time. These approaches are generally tailored to a specific application, providing an application-specific SoC. They deal with the selection of OCI architecture to accommodate the expected applicationspecific data traffic...
In multicore systems, low transmission delay and high throughput are essential to fully harness the computational power offered by tens or hundreds of cores. In this paper we present a new NoC architecture (M8NoC) by devising changes to the topology and routing of the simple mesh network. The changes allow overcoming some limitations of the mesh network by decreasing the diameter, decreasing the average...
Network-on-Chip (NoC) Router has an important impact on the network communication performance. High performance router will help to build a high-throughput, power-efficient and low-latency NoC. However, the existing baseline router of Triplet-based Hierarchical Interconnection Network (THIN) can not fully exert the potential performance of THIN because it does not consider the characteristic of THIN...
Future processors are expected to be made up of a large number of computation cores interconnected by fast on-chip networks (Network-on-Chip, NoC). Such distributed structures motivate the use of message passing programming models similar to MPI. Since the properties of these networks, like e.g. the topology, are known and fixed after production, this knowledge can be used to optimize the communication...
Performance of the network is measured in the term of throughput. The throughput and efficiency of interconnect depends on network parameters of the topology. Therefore, topology of any communication networks has an important role to play for efficient design of network. This paper considers the design of efficient topology based on binary trees structure. We have obtained degree of proposed topology...
The demand for faster processors having high processing capability over area ratio is increasing. The topologies play a major role in the area and network latency. In this paper, we have investigated scope for extending 2-D topologies for 3D network-on-topologies. Most recently, chips with 64 or more processors have already been developed in 2D-networks [7, 9]. In this paper, we discuss many more...
This paper proposes square topology as an efficient topology for Network-on-Chips (NoCs). Although the proposed topology imposes the cost near to that of the mesh topology, the proposed topology 1) provides lower diameter for NoC, 2) offers better performance under uniform and hotspot traffic pattern. In our simulation, the proposed square topology had better performance in comparison to other topologies...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.