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In this paper, a high-speed low-power full adder design using multiplexer based pass transistor logic featuring full-swing output is proposed. The adder is designed and simulated using the industry standard 130 nm CMOS technology, at a supply voltage of 1.2 V. The obtained Power Delay Product (PDP) of its critical path is 29×10−18 J and its power consumption is 2.01μW. The proposed full adder is also...
In this paper, a new Ultra low voltage (ULV) logic circuit based on the floating gate structure is presented. In this technique we utilized the bulks of the transistors to speed up the circuit. Using the proposed method, the speed of the circuit enhances by connecting the bulks of the evaluating and recharge devices to the clock, power supply (VDD) and input signals. The simulation results for the...
High speed analog to digital converters (ADC), memory sense amplifiers, RFID applications, data receivers with low power and area efficient designs has attracted a wide variety of dynamic comparators. This paper presents an improved design for a dynamic latch based comparator in achieving higher speed of conversion targeting 8-bit asynchronous successive approximation register (ASAR) ADC. The comparator...
This paper presents the full zero voltage switching three-level boost dc-dc converter. The boundary conduction mode and snubber capacitors provide zero voltage switching operation in the whole range of operation. Analytical estimation and simulation results have proved the proposed idea. In advance, it was demonstrated that the multi-cell structure along with an interleaved control technique provide...
A new three phase three transistor voltage source inverter has recently appeared in the literature which has attractive features compared to the conventional voltage source inverter topologies. In particular, it requires a less number of costly switching devices, such as high performance transistors. This inexpensive design is considered to be advantageous in medium to high power application requiring...
In this paper, we propose a level shifter circuit that is able to convert signal levels of subthreshold values to super-threshold signal levels. Such a circuit is using a new voltage level shifter topology employing a level-shifting capacitor. This capacitor is charged only when the logic levels of the input and output signals are not corresponding to a high-to-low transition of the input signal....
In this paper, an electronically tunable current-mode quadrature oscillator employing three current follower trans-conductance amplifiers (CFTAs) and two grounded capacitors is proposed. The use of all grounded capacitors makes the proposed circuit ideal for integrated circuit implementation. The circuit provides two high-output impedance current signals with 90° phase difference. It condition of...
In this paper we consider the numerical simulation TCAD Sentaurus of the vertical NPN and PNP transistors fabricated on complementary bipolar technology with a P-epitaxial layer. As a result, technological parameters associated with the buried and epitaxial layers have been defined. These parameters have provided the required voltage value of collector-emitter breakdown. The comparison of the transistor...
One effective way to reduce the power consumption of biomedical implantable devices is to employ different supply voltages for different parts of the system depending on the processing speed of each part. This, however, necessitates the use of voltage level converters. This paper presents a power-efficient voltage level-shifting architecture that is capable of converting low levels of input voltages...
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 25% reduction of power consumption is achieved by the proposed unit. In the 32/33...
We investigate the impact of single-event upsets in dynamic flip-flop circuits, which are more appealing for the design of high-performance microprocessors because of short latency, small area and high clock frequency. Previous work either uses the approaches for static flip-flops to evaluate SEU effects in dynamic flip-flops or overlook the SEU injected during the precharge phase. We re-examine the...
In this paper, we introduce an efficient method to control the propagation stopping condition locally for asynchronous binary propagation networks. Additional switches are introduced to the Wired-OR pull-down path branches, where the switches are controlled by the PE outputs from the neighborhood. An example for a 1-D case for object center pixel extraction is given with simulation results for asymmetric...
This paper presents, we present a novel method for CMOS implementation of programmable gaussian fuzzifier. Utilizing the proposed mechanism, only one transistor is required to control the slope of the generated Gaussian membership function. Comparing to some other works in the literature, the proposed circuit requires lower power consumption as well as low circuit area, which makes this structure...
Carry select adder (CSLA) one of the fastest adders used in complex data processing to perform fast arithmetic functions. Minimum amount of power consumption is a major driving force behind the development of CMOS technologies. From the structure of CSLA it is clear that there is scope for reducing the area & power consumption in the CSLA. In this paper 8T full adder is used as a building block...
In order to achieve the prediction of the phase noise of low phase noise crystal oscillator, based on the classic phase noise model of Leeson, the load Q value (QL) is calculated according to the selected oscillator circuit parameters. Thus, on the basis of Lesson phase noise formula, the predicted results of the phase noise of low phase noise crystal oscillators are obtained. Then, the nonlinear...
In recent years, reversible computation has received much attention in the field of low power circuit design. In this paper, an irreversible IG-A gate is presented. The gate is further used to design irreversible full adder/subtractor (IAS). Furthermore, IAS block is utilized to construct n-bit adder and subtractor. Proposed IAS design is analyzed and compared against the existing reversible methods...
In this paper, a fully differential difference amplifier designed in 0.35 µm CMOS technology is presented. The proposed amplifier reaches high dynamic range and low input noise. Comparison of noise performance of the proposed fully differential difference amplifier to an ordinary differential amplifier has been performed. Simulation results prove that the developed amplifier circuit can be advantageously...
In this paper, we present high voltage NLDMOS structure with multiple RSEURF concepts. The NLDMOS is based on 0.35µm BCD process. The multiple RESURF device base on charge balance theory using P-top and N-top to achieve high breakdown voltage and low on-resistance. The 2D simulation result compares the conventional single RESURF NLDMOS structure and the new structure with multiple RESURF devices....
We report a two-dimensional simulation study of a dopingless TFET with a hetero-gate dielectric. The energy band gap on the source side is modulated using a hetero-gate-dielectric in a dopingless TFET to increase the source-side tunneling rate. The use of a hetero-gate-dielectric, only on the source side, will ensure that the ambipolar current is not enhanced due to the drain-side tunneling. We demonstrate...
From the past few years a variety of low power adders have been proposed to reduce the overall power consumption of micro-electronic systems. The role of adders are important in almost all fields of engineering and applied sciences. With the help of low power adders, all the other systems which make use of adders may dissipate less power. This study presents a detailed comparison between various low...
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