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A low drop-out (LDO) voltage regulator with high power supply rejection ratio (PSRR) and enhanced transient response is presented in this study. The proposed idea is to apply a replica circuit that injects current into the second stage of the error amplifier. The LDO is being fabricated in Magna Chips CMOS Technology. The regulated output voltage of the LDO is 1V with the power supply voltage of 1...
To improve the performance of typical first-order bandgap references, a high precision bandgap voltage reference with second-order curvature correction is proposed in this paper. Utilizing a temperature independent current (has nothing to do with the temperature of first order) and a proportional to absolute temperature (PTAT) current, a proportional to the square of temperature (PTAT2) current can...
A bulk-driven operational transconductance amplifier (OTA), which adopts the chopper stabilization technique to attenuate the flicker noise and offset, is proposed in this paper. Operating in the subthreshold region, the chopped bulk-driven OTA has the abilities to work in low-voltage condition, thus consuming only nanowatt power. The circuit was simulated on UMC 180 nm CMOS process. Simulation results...
A comprehensive simulation analysis method is proposed to improve the bottom select gate (BSG) transistor's Vth distribution by adopting under-channel implant in this work.
An area and power-efficient modular mixed-signal synapse architecture is proposed for VLSI implementation of the multi-layer feed-forward neural network. The proposed circuitry multiplies synaptic weights that are stored in digital registers with the analog input. The multiplication result is always an analog current. Despite conventional MDACs principle in which all the multiplication work is performed...
This paper presents novel bulk-driven current mirror and bulk-driven cascode current mirror. Bulk-driven technique is employed to overcome a threshold voltage limitation. High accuracy transfer characteristic over wide current range is achieved through a negative feedback. The proposed circuits are designed and simulated with a 0.18 μm CMOS technology. They operate at 1 V power supply. The simulation...
Approximation in the adder logic is a promising solution for energy-efficient designs in various applications. In this study, new hybrid adder design, which consists of an accurate adder for higher bits and proposed approximate adders for lower bits, is investigated. The XOR-based inexact adder is modified to be used in the approximation part. Simulation results of 16-bits adders show that error rates...
This paper presents an optimization method of area and power for static memory elements by using multi-mode power gating (MMPG) scheme. A 2-transistor MMPG scheme replaces the usual 5-transistor one to effectively reduce on chip area overhead and leakage power, simultaneously combining trimming circuits (TC) to guarantee the safety of data retention. When applying the proposed approach into clean/dirty-cache...
Models of Synchronous Generators with PWM DC-DC converter and Self-Excitation Systems have been designed. Calculations have shown that the unipolar PWM DC-DC converter in some modes shortly excludes from the voltage regulation process. The bipolar PWM converter effectively affects the generator and consequently enhances the system operation speed. The bipolar PWM converter uses the energy recovery...
In this paper, an investigation of the behaviour of a high step-up DC/DC converter is conducted as an application in a Static Waste Heat Recovery System (SWHRS) for ships with DC bus. It is proven that a higher step-up ratio can be achieved with the proposed DC/DC converter compared with that of a classical step-up converter, even in a high power level. Also, analysis of the proposed Waste Heat Recovery...
Technology scaling has been aggressively developed during last several years and almost close to the final states. In order to cope with high density new technology, silicon based memory cell also needs to be replaced by alternate devices. Memristor is one of the promising novel elements for memory cell. This paper proposes a new memristor based hybrid memory cell, which is capable of bidirectional...
The Advanced Encryption Standard (AES) is the current world standard symmetric key block cipher cryptosystem for data encryption/decryption. Multi-valued logic (MVL) is a propositional calculus that goes beyond binary in terms of the number of truth values. There has been intensive research work conducted attempting to enhance the performance of cryptographic systems in terms of speed and area. We...
Adders are one of most essential components of the digital circuits that are designed for different DSP applications. The important aspects considered for designing any digital circuit design are delay, power and Power Delay Product (PDP). In this paper, 32 bit carry bypass adders (CBA) which have superior performance with respect to these parameters are presented. The CBA's are implemented using...
A study of current efficiency for CMOS class-B and class-C LC oscillators working in triode region is presented in this paper. Using Fourier-transform analysis and rigorous mathematical deduction, closed form expressions describing current efficiency are derived for class-B and class-C LC oscillators. Simulation results have been run in Cadence SpectreRF using 0.13-um standard RF CMOS technology,...
In this paper SIMSIDES-based (Simulink-based Sigma Delta Simulator) high level simulation of a 4th order Hybrid ΣΔ Modulator was carried out to find the performance requirements of several Analog Building Blocks (ABB). Once the requirements have been defined, the next step is to design each ABB at the transistor level. One of them, a fully differential OTA, was sized through a Design of Experiments...
A new high-voltage-tolerant level shifter is proposed and verified in a 0.18-µm CMOS process with 1.8-V/3.3-V devices, whereas the operation voltage can be up to 12V. The output signal of high-voltage-tolerant level shifter has an offset of 3 times the normal supply voltage (VDD) of the used technology with respect to the input signal. The converting speed of level shifter is improved by using the...
A novel aperture error reduction technique for subrange successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. By reusing capacitors of flash ADC during fine conversion phase, thermometer coarse capacitors belonging to CDAC can be removed from the circuit. Compared with the conventional subrange SAR ADC without front-end T/H, this technique can minimize...
In this paper, a new active-only integrator which can be used to realize low frequency filters with small chip area is presented. The circuit can be effectively implemented using transconductance elements and its integration frequency is electronically controllable. In order to illustrate its usefulness, a second-order multifunction filter with low cut-off frequency, yet which occupy a small chip...
In recent years, the three-phase pulse width modulation controlled voltage source converter (PWM-VSC) has found its way to wide range of applications, among which renewable energy sources and adjustable speed drives are the most common. In order to achieve low harmonic distortion of current at the point of common coupling (PCC), LCL filters are used for grid connection since they ensure higher damping...
Increasing power density of high-switching frequency power modules presents a heat transfer challenge that left unaddressed can cause module failure. The first step in addressing this challenge is to estimate the maximum temperature that is observed in the module. PowerSynth, a multi-chip power module layout synthesis tool, utilizes a fast thermal model to quickly determine the steady-state maximum...
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