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Now-a-days On-line testing becomes an indispensable part of DFT (design for testability) for detecting rapidly increasing intermittent faults in deep sub-micron ICs. Much of the proposed on-line testing techniques are for synchronous circuits as compared to asynchronous circuits. The existing online testing(OLT) techniques of asynchronous circuits involve development of checkers that verify the correctness...
With the increasing complexity of VLSI circuits and systems, their testing is becoming increasingly complex and time consuming. Apart from affecting the design turn-around time, it poses severe challenges to the test engineers in terms of meeting the power-budget and temperature limit of the chip. Power consumption during test is often much higher than in normal mode of operation. Increasing temperature...
QCA (Quantum-dot Cellular Automata) is the promising future nanotechnology for computing. In QCA, the cells must be aligned properly at nano scales for proper functioning. Defects may occur in synthesis and deposition phase. So the defect analyses and testing cannot be ignored. This paper presents a survey on QCA basics, defect characterization and various testing aspects of QCA.
The present work deals with a fault tolerant approach to design the test structure for detecting the fault of cache in chip multiprocessors (CMPs). Fault detection is simplified using a 2-state 3-neighborhood null boundary cellular automata (CA). This has been elaborated in the earlier work of present authors. Self correcting property, however, has been found only in a 5-neighborhood CA and not in...
IEC61850 is widely accepted around the globe due to the significant benefits that it provides compared with conventional hard-wired solutions. In this paper, four different IEDs from three different vendors (ABB, Areva and SEL) namely: REF615, SEL487, SEL311 and P145, are used to model a bay level of IEC61850 substation. Then, using industry standard fault test simulator “CMC356 OMICRON”, different...
Testing and diagnosis of analog circuits are very important tasks at the quality assurance of integrated circuits and electronic devices. Faults detection and identification are realized using fault dictionary. The architecture of fault dictionary has an essential influence on time and efficiency of diagnosis at whole. An approach to the construction of fault dictionary as the neuromorphic classifier...
Reliability of power electronic systems is of paramount importance in industrial, commercial, aerospace, and military applications. Faults in power converters are classified as short circuit faults, open circuit faults, and degradation faults. Short circuits (S-C) in most cases cause an overcurrent condition that is readily detected and acted upon by standard protection systems. However, open circuit...
The paper suggests integrated impedance based intelligent relaying for thyristor controlled series capacitor (TCSC) compensated transmission lines. The scheme uses a new relaying signal termed as imaginary part of integrated impedance (IPII). Integrated impedance is defined as the ratio of sum of the voltage phasors across two ends of the transmission line to the sum of the current phasors through...
Mutual exclusion elements (MUTEXes) are fundamental components of asynchronous arbiters and are particularly critical to ensure metastable signals are properly filtered before reaching the arbiter outputs. However, despite their importance, the testability of these circuits is typically limited to functional testing. This paper discusses why this is not sufficient and addresses testability issues...
Power-related problems in at-speed scan testing have become more and more serious, since excessive IR-drop caused by excessive power consumption results in overtesting. There are two important factors in low-power testing: one is power estimation, the other is power reduction. Several estimation methods have been proposed based on the analysis of switching activity characteristics. In order to estimate...
The development of the single-core symmetrical phase shifting transformer (PST) model and testing results of its selected differential protection is described in this paper. Generally, a PST is used for controlling the active power between the two systems being connected with one or more parallel transmission lines (paths). Most types of PSTs allow for changing of phase shift in a certain pre-defined...
In this paper a test method for MEMS devices is presented in which physical defects are detected in the frequency domain rather than the time domain. A resonator, that can be part of a read out circuit, is utilized to test capacitive Micro-Electro-Mechanical Systems (MEMS). The proposed technique is based on the principle of resonant frequency where variations of the resonant frequency are observed...
This paper presents a novel approach for performing diagnosis in test access mechanisms (TAM) architectures based on time domain multiplexing and serial scan shifting. These TAM architectures allow efficient application of low power compressed patterns to individual embedded cores present in SoCs using limited pins. The proposed diagnosis approach relies on the connectivity information of the TAM...
Microfluidic biochips are replacing the conventional biochemical analyzers by integrating all the necessary functions for biochemical analysis using microfluidics. Biochips are used in many application areas, such as, in vitro diagnostics, drug discovery, biotech and ecology. The focus of this paper is on continuous-flow biochips, where the basic building block is a microvalve. By combining these...
The test complexity of high density DRAMs increases with technology evolution, due to a larger impact of process variation and weak defects. In particular, resistive open defects turn to be a major concern in DRAMs. Our analysis and simulation results show that an important phenomenon exists, charge accumulation, which is currently not considered in DRAM testing. Charge accumulation occurs in DRAM...
The temperature of a block (a region in the chip) depends on both heat generation (caused by power consumption) and heat dissipation among neighbors. Power aware test solutions targeting low power consumption during testing, may not produce an acceptable thermal aware solution. In this paper, a hardware based solution using an AND-OR block between the decompressor and each scan chain, has been utilized...
This research describes an approach to test metastability of flip-flops with help of multiple at speed capture cycles during path delay test. K longest paths starting from a flip-flop are generated, such that a long path on one clock cycle feeds a long path on the next clock cycle, and so on. This permits the testing of flip-flop metastability and time-borrowing latches, that cannot be tested by any...
In this paper a new method is presented to automatically generate a Design-for-Testability infrastructure which increases the observability of defects in integrated circuits. An algorithm is proposed to detect circuit locations to which small detection blocks can be added. Those are coupled to an oscillator and the triggering of this oscillator in case of detected defects leaves traces in the power...
Code-based test vector compressions are the most capable of testing current SOCs consisted of a large number of IP cores because they do not need the structure information of the cores. However, the compression ratios of this kind of compression approaches are often lower than that of other compression methods, such as linear-decompression-based schemes and broadcast-scan-based schemes. In this paper,...
Ever smaller nanotechnologies introduce new types of defects and fault mechanisms with negative influence on system on-chips (SoCs) reliability and operational life. This paper presents a fault diagnosis and repair procedure which is implemented into generic built-in self-repair architecture. The procedure utilizes on-line fault detection whereas repair is performed during off-line mode. Experimental...
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