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An approach to test application called transparent scan provides an opportunity to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. The conventional methodology suffers from problems such as high power consumption, less quality results both in terms of pattern count and fault coverage...
Software systems are more and more complex. They are usually constructed by combining several components which can be implemented separately and deployed in distributed environments. This paper presents a framework for testing these kind of systems. Particularly, each component of a system is tested by a tester and there is no communication between testers. The tester is guided by local test cases...
The time synchronization among simulation federates could be realized through logical time by traditional time management of distributed simulation. There are two types popular time management of distributed simulation based on logical time, conservative time advance mechanism and optimistic time advance mechanism. Conservative time advance mechanism restricted the causal relationship between simulation...
PHY layer authentication of a wireless sender has gained much interest recently. In this paper, we consider the famous Alice, Bob and Eve model and investigate (for the first time) the feasibility of using time-varying clock offsets for sender-node-authentication at Bob. Specifically, we exploit the fact (and de-facto problem) that clock offset between every node pair is unique; moreover, the two...
This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order...
Scan based transition delay fault (TDF) tests are generally applied in the launch-on-capture (LOC) mode because the scan enable control signal broadcast to all flip-flops on the die is expensive to implement as a fast switching signal needed to support at-speed launch-on-shift (LOS) tests. However, there is mounting evidence that even when applied at much slower speeds, LOS tests often detect a significant...
In this paper we will describe a solution to test I/O cells that use four level pulse amplitude modulation (PAM-4) at data rates of 32 Gbaud using a commercial ATE platform without any external instruments. The solution is based on an active test fixture where a retimed digital to analog converter (DAC) is used to generate the PAM-4 stimulus signaling. The comparator side is implemented using a single...
Reconfigurable systems are increasingly employed in many application fields, including aerospace. The long term exposure to radiation of space electronics can cause permanent faults, that may lead to the failure of the mission. In this paper we present a novel technique for on-line on-demand testing of permanent faults in the routing structure of SRAM-based FPGAs, that are employed in reconfigurable...
This paper proposes a structure for a digital coder, optimizing the multiplication circuit area that leads to a substantial gain in the main circuit surface and helps future decoding. The work describes the functioning process, the technical design and tests the coder's main functions. The evolution of RS coding and the growing pallet of application domains are also briefly covered.
Vector dot product is an important computation which needs hardware accelerators. We present an optimized accelerator chip that has larger capacity than our prior designs. This design can compute product for 10000 component vectors within 1000 clock cycles, with average being 80 cycles. Our design has superior speed compared to other accelerators.
Architectural models, such as those described in the east language, represent convenient abstractions to reason about automotive embedded software systems. To enjoy the fully-fledged advantages of reasoning, EAST-ADL models could benefit from a component-aware analysis framework that provides, ideally, both verification and model-based test-case generation capabilities. While different verification...
Digital micro fluidics based biochips is expected to play an important role towards point-of-care diagnostics, drug discovery, prevention of bio-terrorism and other biochemical applications. Design and testing of biochips always remained a challenging area of research. Structural testing of these bio-MEMS is ensured by smooth movements of test droplets within the micro fluidic array. Partitioning...
As a result of the recent advancements in technol-ogy, FPGAs are more often used for automotive applications. They must therefore meet industrial requirements like a fast and very low cost fault detection strategy for their configuration memory. Cyclic memory tests are the state of the art approach for this task. They do, however, violate fault detection times, especially for the latest FPGA devices...
Software plays a dominant role in modern automotive systems. The rapid increase of automotive software brings various challenges for automotive system development. To ensure the safety and reliability of automotive software systems, new methods, models and tools are used in the software development. In this paper, we propose an approach of source code testing for automotive software by use of the...
Asynchronous design is predicted to have a significant place in the future due to benefits of speed, power consumption, and design. Null Convention Logic (NCL) is a subcategory of asynchronous design that results in the most reliable and low-power asynchronous hardware. However, test strategies are not adopted to match the characteristics of this important asynchronous method, and the existing test...
Dynamic voltage scaling (DVS) combined with the partitioning of the System-on-Chip (SoC) into multiple voltage islands constitutes a powerful dynamic-power minimization technique. However, the sharing of the test-access mechanisms (TAMs) among different voltage islands, the necessity to test every core at multiple voltage levels and the low shift-frequency limits at the lower voltage levels introduce...
This paper proposes a new multi-channel testing architecture for high-speed eye-diagram. The proposed architecture reconstructs the eye-diagram of a multi-Gbps bit pattern with the combination of pin electronics and reconstruction algorithms. A scalability of the test system significantly increases in behalf of a monobit receiver and its designated reconstruction algorithm. A novel reconstruction...
Interposer-based 2.5D integrated circuits (ICs) are seen today as a first step towards the eventual industry adoption of 3D ICs based on through-silicon vias (TSVs). The TSVs and the redistribution layer (RDL) in the silicon interposer, and micro-bumps in the assembled chip must be adequately tested for product qualification. We present an efficient interconnect-test solution that targets TSVs, RDL...
Jitter is a crucial factor in high speed and high performance ADC testing. This paper proposes an efficient and accurate jitter estimation method based on one frequency measurement. Applying simple mathematical processing to the ADC output in time domain, the RMS of jitter and noise power are obtained. Furthermore, prior information of harmonics does not need to know before the processing. The algorithm...
The introduction to the use of Field Programmable Gate Arrays in a first year course of digital design is nowadays advisable. A self-developed tool that integrates FPGA configuration and testing within Deeds, the simulation suite upon which the course is based, makes the full process straightforward and compatible with the beginners' skills. The tutorials that accompany the students' projects provide...
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