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Potential faults in safety critical systems may lead to system failures thus bring huge human injuries. How to ensure the correctness of the system during the system development is very important. System function testing has been regarded as an effective approach which normally applied in the final stage of system development to ensure the consistence of system functions and specifications. In this...
As distributed systems such as automotive, medical, manufacturing automation become larger and more complex, it is difficult to test these systems. Also, the synchronization of distributed applications make the testing more difficult. In the Software-in-the-Loop (SiL) simulation, a synchronization method among clock of applications is provided for virtual hardware devices and environment. A typical...
This paper presents a scalable time optimized online test solution that addresses short faults in interconnects of an on-chip network (NoC) and observes the deep impact of these faults on NoC performance at large traffics.
The recently proposed three-dimensional (3D) integration promises to enhance the system performance. However, it poses several test challenges. Thermal safety of the 3D system is the foremost concern. Testing of the system plays an important role to improve the yield. This work presents a thermal-aware core test scheduling technique in 3D stacked multicore system using Particle Swarm Optimization...
Functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over-as well as under-test issues. This work is based on the use of Software-Based-Self-Test that allows a special application of functional test to the processor-based systems. This strategy applies the so-called functional test programs that are executed by the processor to guarantee a given fault coverage...
This paper is about conformance testing of non-deterministic timed pushdown automata (TPAIO), with urgency modelled as deadlines put on the transitions. The deadlines impose time progress conditions (TPC) on the locations of the TPAIO. In addition to detecting non conform or out of the time limits outputs of an implementation, our tests also detect TPC violations. Our method proceeds by a one-clock...
Several literatures focused on self-testing of digital and analog integrated circuits. They proposed different test scenarios for the circuit board based on the signature analysis. The single-shot (SS) circuit is important element on the circuit board level in the industrial applications. In this paper, a new testing design is presented to functionally test the SS circuit on the circuit board. It...
Interdependence of the clocking architecture across IPs and overall peak power consumption is a major bottleneck that prevents concurrent yet independent testing of an IP at a higher clock frequency. We use a dynamic clocking architecture that eliminates these dependencies and reduces peak shift power by using clock phase staggering at a granular level during system-on-chip (SoC) testing. A SoC design...
A new methodology for extracting compact test stimuli from functional tests for infant mortality testing of analog circuits is proposed. The test stimuli are extracted such that they produce extremal electrical activity in the circuit to push latent defects over the edge to become hard defects. Results on analog modules from the receiver sub-system of a high speed serial interface show that tests...
Testing for small delay defects (SDDs) is important due to their dominance in recent technology nodes. Unfortunately, all the SDD test quality metrics in the literature limit their assessment to the size of the delay defect tested under at-speed or slower clocks, which makes their results misleading under special cases such as faster-than-at-speed testing. Moreover, those metrics are inadequate for...
We present a programmable method for shift-clock stagger assignment to reduce power supply noise during system-on-chip (SoC) testing. An SoC design is typically composed of several blocks and two neighboring blocks that share the same power rails should not be toggled at the same time during shift. Therefore, the proposed programmable method does not assign the same stagger value to neighboring blocks...
At-speed testing of deep-submicron or nano-scale integrated circuits (IC) consumes excessive power and creates hotspots and temperature gradient in the chip-under-test. The problem worsens for 3D ICs, where heat dissipation across layers is more unbalanced. These hotspots in a circuit often cause severe degradation of performance and reliability, as a rise in temperature can introduce an extra delay...
Spread-spectrum is a technique which is widely used in telecommunication and radio communication. For clock signal, this technique makes the clock signal energy distributed on the relevant frequency range rather than on the single frequency point. Thus the Electro-Magnetic-Interference (EMI) of clock is reduced. Since the clock signal is modulated by another signal, resulting in its frequency is changing,...
Heavy-ion beam is used to perform Single Event Effects testing on the Flash-based and radiation hardened FPGA, the RT4G150 device. Soft errors due to SEU and SET in the fabric Flip-Flops and PLL generated clocks are measured and analyzed. SEFIs in PLL and SERDES are also observed.
System-on-Chip (SOC) designs composed of many embedded cores are ubiquitous in today's integrated circuits. Each of these cores requires to be tested separately after manufacturing of the SoC. That's why, modular testing is adopted for core-based SoCs, as it promotes test reuse and permits the cores to be tested without comprehensive knowledge about their internal structural details. Such modular...
Excessive power consumption during testing has been one of the most important issues from the exponential advance in semiconductor manufacturing technology. In this paper, a scan segment skip technique is proposed to reduce power consumption by skipping segments that don't need scan in/out processes. Also, a new pattern merge algorithm is proposed for maximizing power reduction ratio. Experimental...
IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of...
The increasing power consumption during the chip testing process has become the bottleneck of chip production and testing for micro-nano VLSI circuits. Numerous low power design-for-testability (DfT) techniques have been proposed to deal with the test power problem, and segmented scan method was shown to be an efficient solution. We propose a new poweraware scan segment architecture, which can accurately...
In three-dimensional (3D) integrated circuits (IC-s), many clock-TSVs are deployed to deliver clock signals to different tiers with minimum skews. However, these clock-TSVs are prone to aging effects, such as thermal-mechanical stress and electromigration, rendering hard-to-predict clock skews at runtime. These skews have a wide range of influence on the flip-flops, and may violate the safety margins...
Coordination is playing a key role in complex cyberphysicalsystems (CPSs). The complexity and importance of coordination models and languages for CPSs necessarily lead to a higher relevance of testing during development of CPSs. Model-based testing is a promising technology to test the conformance or non-conformance relation between the implementation-under-test (IUT) and its specification. In this...
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