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In access-network-chip testing and verification, problems occur mostly on I2C control interface because of its complicated protocol and high requirement on reliability, using an automated testing tool with simple operation and high testing coverage could ensure the quality of chip as well as shorten the chip development cycle. The paper designs an automated system based on 5SGXEA7N2F45C2 FPGA chip...
Managing the power consumption of circuits and systems is challenging not only during functional operations but also during manufacturing test. This paper discusses industrial practices in this area. It is organized into three main parts. First, we give necessary background and discuss issues arising from excessive power dissipation during test application. Then, we provide an overview of industrial...
This paper describes a low-cost extension module used to extend an FPGA-based development platform that enables digital testing up to 40Gbps. This platform typically operates up to 13.1Gbps and can be applied to test current main-stream I/O standards such as PCIE3.0 (8Gbps), USB3.1 (10Gbps) and Thunderbolt (10Gbps). The high bandwidth of an ultra-high-speed test module allows testing capability for...
Semiconductor industry has been putting tremendous efforts on 2.5D technology in accordance with the increasing demand for better capacity and system performance. This technology enables several dies to communicate up to the speed of Gigabits per second while reducing the cost for a system with heterogeneous components. However, such new technology also poses great challenges whereby the manufacturing...
The article presents 12.5 Gbit/s Physical Media Attachment (PMA) units, TX and RX, fabricated in 90 nm bulk CMOS process. The PMA are designed for use in SpaceFibre/GigaSpaceWire (SpaceWire-RUS) systems for the space radars. The units comprise SERDES and clock and data recovery (CDR). Supported set of data rates includes those of 1.25, 2.5, 6.25 and 12.5 Gbit/s, but intermediate rates are also available.
Low-power VLSI circuits are indispensable for almost all types of modern electronic devices, from battery-driven mobile gadgets to harvested-energy-driven wireless sensor systems. However, the testing of such low-power VLSI circuits has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper will highlight three major test-power-induced problems (namely...
Lazy sequentialization is one of the most effective approaches for the bounded verification of concurrent programs. Existing tools assume sequential consistency (SC), thus the feasibility of lazy sequentializations for weak memory models (WMMs) remains untested. Here, we describe the first lazy sequentialization approach for the total store order (TSO) and partial store order (PSO) memory models....
Power dissipation is a major issue with testing of designs having full scan architectures. The proposed scan technique minimizes toggle activity while scanning in test patterns. The method uses bit inversion technique to avoid toggles in scan flip-flops. The setup is dynamically configurable to one among the logic reversal structure and traditional scan while shift-in/shift-out of test patterns. Experimental...
Flash memory is widely used in many fields, but there are still some problems with the generation of test pattern. The working and testing method of the memory is complex, for large capacity memory, the workload of generating a test pattern by the method of using manually is prohibitive. And Simulation files may not be obtained from design companies by the reason of protection of intellectual property...
In this paper, we address the problem of deriving test suites for checking components of interacting finite state machines with timed guards (TFSMs). Given a component TFSM, a corresponding test is derived for the composition of TFSMs under the assumption that all other components are fault-free.
Multi-cycle scan-based tests allow more faults to be detected by keeping the circuit in functional mode for more than one clock cycle. Optimizing a multi-cycle test set can improve test quality and/or test application time. It is also possible to capture the primary outputs of a circuit multiple times between the scan operations. This ensures that if a fault is detected at the primary outputs, increasing...
In this paper we consider two properties of timed automata, which help to reduce their complexity. We understand complexity as the number of time variables associated with a given timed automaton. The first property concerns redundant time variables and the second — timed automata composition.
The paper presents some technical issues for testing distributed systems. The proposed approach consists on exploring the temporal properties that specify the time required to exchange messages between the various components of the distributed test application. Thereby taking into consideration the temporal properties in the specification of the behavior of conformance testing, it will provide a higher...
With the ever growing complexity of hardware designs, their functional verification has become quite a challenge. Despite other techniques like emulation and formal verification methods, simulation continues to be the most common and primary technique to functionally verify the hardware design written in Verilog. Due to the limited computational resources, exhaustive testing of the present-age complex...
Modern systems-on-chips rely on embedded instruments for testing and debugging, the same instruments could be used for managing the lifetime dependability of the chips. The IEEE 1687 (iJTAG) standard introduces an access network to the instruments based on reconfigurable scan paths. During lifetime, instruments could be required to initiate communication with a system-level dependability manager for...
This paper discusses radiation tests on complex System-on-Chip (SoC) controllers using Low-Energy Protons (LEPs). The aim of this novel set of guidelines is to be also applicable to System In Package (SIP) or hybrid components that are now often used to overcome printed circuit board's real estate restrictions in Hi-Rel electronics.
In Industry 4.0 nodes are becoming interconnected and part of the growing Industrial Internet of Things. The use of a reduced physical layer and emerging real-time Ethernet standards, enables such nodes to be implemented cost-efficiently. Technologies and standards, which focus on cost-efficient Ethernet technologies for the use in vehicles, are quite promising for industrial applications. The integration...
The single event effects hardening and heavy-ion testing of a radiation-hardened Flash-based field programmable gate array, RTG4, are presented. The hardened logic circuits include fabric flip-flops, fabric SRAM, global clocks, PLL, and SERDES. SEL is hardened for the whole chip. Lastly, the inspace programming is hardened as the consequence of the above hardening activities. Test results show the...
The GR718B is a radiation tolerant 18-port, standalone, SpaceWire router developed by Cobham Gaisler AB for space applications. The validation of the most critical design blocks of the SpaceWire router with respect to Single Event Effects, when operated at high frequencies, is reported herein. In addition, the insensitivity of the design library used for the development of this device to Single Event...
The paper discusses step-by-step practical flow involved in applying dynamic bandwidth management (DBM) to large industrial system-on-chip (SoC) designs deploying embedded test data compression.
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