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Three-dimensional (3-D) integration is an emerging integrated circuit technology. It offers many advantages over the 2-D integration. However, testing 3-D chips is a very challenging job. The testing of a 3-D chip includes the testing for known good die (KGD) and the testing of stacked 3-D chip. This paper analyzes the test complexities of 3-D random access memories (RAMs) and content addressable...
This paper presents very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin film transistor (a-Si TFT) technology. The proposed VLV testing is an economic alternative to burn-in because the former is non-destructive and can be easily performed on regular ATE in a short time. 140 circuits under test (CUT) of two different design styles are implemented in 8 mm a-Si TFT...
This paper presents a leakage characterization technique for switched capacitor (SC) integrators. It is a low-cost on-chip solution because (1) the test stimulus is a DC voltage whose exact value is not important, and (2) the output response digitizer is simply a comparator. Simulation results show that integrator leakage can be accurately characterized even in the presence of noise and comparator...
Same output frequencies at each DUT of the testing circuit are multiplied by different LO frequencies signals at mixers stages, which different frequency-translated spectrums were captured at capture port simultaneously for achieving fully parallel test of RF device.
This work proposes a methodology to minimize the application cost of outlier analysis when applied to delay testing in the presence of systematic variability. Support vector machine (SVM) outlier analysis algorithms and traditional entropy measures are used to detect delay defects by choosing a minimum number of suitable test clocks. Monte Carlo simulations generate realistic test data while information...
This paper proposes a self-calibrating approach for embedded RF down-conversion mixers. In the proposed approach, the output of the RF mixer is analyzed by using on-chip resources for testing and the mixer performs self-compensation for parametric defects using tuning knobs. The tuning knobs enable the RF mixer to self-calibrate for multi-parameter variations induced due to process variability. Using...
Test mode power dissipation has been found to be much more than the functional power dissipation. Since dynamic power dissipation had a major contribution to the heat generated, most of the studies focused on reducing the transitions during testing. But at submicron technology, leakage current becomes significantly high. This demands a control on the leakage current as well. In this work, we propose...
With the changing face of the consumer driven semiconductor industry, there are new challenges facing the industry which need to be resolved. Minimizing power dissipation is a significant and growing challenge with the growth of the wireless and portable device segments and with the need to be `green'. Even during manufacturing test, power is definitely among the top ten items needing attention and...
Scan technology carries the potential of being misused as a ??side channel?? to leak out the secret information of crypto cores. To address such a design challenge, this paper proposes a design-for-secure-test (DFST) solution for crypto cores by adding a stimuli-launched flip-flop into the traditional scan flip-flop to maintain the high test quality without compromising the security.
This paper describes a low cost test technique for testing Analog-Mixed Signal and RF load boards used in ATE (Automatic Test Equipment). The paper describes the development and application of a software tool for automatic analysis and test generation for mixed signal and RF circuits on Device Interface Boards (DIB). DIBs are essential components for testing ICs and they contain mixed-signal and RF...
This paper presents the test instruction set architecture (TISA), an invention that can enable scalable interactive testing to leverage the experience of embedded computing. This approach is applied to an 1149.1 system, obtaining a processor able to efficiently handle instrument-based operations.
A technique is described for testing the I/O interfaces of a microprocessor through the use of cache-resident self-test. Experimental results show that this test application method executes much faster than traditional scan-based testing for both characterization and production versions of the tests. The addition of on-chip post-processing of test results further enhances the speedup. The method is...
Homogeneous manycore systems that contain a large number of structurally identical cores are emerging for tera-scale computation. To ensure the required quality and reliability of such complex integrated circuits before supplying them to final users, extensive manufacturing tests need to be conducted and the associated test cost can account for a great share of the total production cost. By introducing...
This work proposes a novel ATE test approach to decrease RF testing yield loss. Background noise of the system-under-test is surveyed based on a prototype load-board equipped with a PCB antenna system to analyze the correlation between the test data and background noise in order to identify the root causes of yield loss. Experimental results of RF testing in the EMI environment correlate well with...
Growing test data volume and excessive test power consumption in scan-based testing are both serious concerns for the semiconductor industry. Various test data compression (TDC) schemes and low-power X-filling techniques were proposed to address the above problems. These methods, however, exploit the very same ??don't-care?? bits in the test cubes to achieve different objectives and hence may contradict...
Several techniques are used to detect defects in digital integrated circuits. Among these techniques is transient current testing (iDDT). The detection capability of iDDT degrades as the size and switching activity of the circuit under test (CUT) increases. In this paper we present clustering techniques that control the switching activity of one cluster in response to applied test vector-pairs. Our...
In this paper, we present a novel integrated method for testing gate-oxide shorts due to pinhole defects in the gate oxide of CMOS circuits using a wavelet transform-based transient current (iDDT) analysis technique. Wavelet transform has the property of resolving events in both time and frequency domains unlike Fourier transform which decomposes a signal in frequency components only. The proposed...
Power-aware X-filling is a preferable approach to avoiding IR-drop-induced yield loss in at-speed scan testing. However, the quality of previous X-filling methods for reducing launch switching activity may be unsatisfactory, due to low effect (insufficient and global-only reduction) and/or low scalability (long CPU time). This paper addresses this quality problem with a novel, GA (Genetic Algorithm)...
March tests have been found to be very effective for fault detection and diagnosis in memories. Effectiveness of a March test is usually decided by the number of faults that can be detected using the test. The more the number of fault models covered, the better the test. March tests with good fault coverage have been developed but the test power also plays an important role in deciding the effectiveness...
In general, CPU may upgrade its frequency by the PLL (phase-locked loop), but the cost of testing is very expensive for high frequency signals. This paper introduces the method that inserts test logics in the CPU to implement its PLL performance testing. It is very easy to implement, and reduces effectively test costs in the case of low hardware overheads. The result shows that the test logics can...
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