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Based on accumulator, a general testing approach for DSP data path and algorithms suitable for the scheme to supply test patterns efficiently are proposed. For the scheme, DSP data path is classed into orders according to structural similarity, and then the building modules with identical connections in one order are partitioned into one layer. Finally, testing of the data path is performed under...
The field of photovoltaic (silicon solar cells) is an important driver for regenerative energy techniques. The technology and efforts regarding efficiency factor, quality, and costs are still under development. Currently, typical silicon solar cells are connected to so called strings by two or three solder coated copper ribbons. The common interconnection technology of silicon solar cells is soldering...
In this paper, an ordinal optimization (OO) based algorithm is applied to minimize the overkills under a tolerable level of re-probes in a wafer probe testing process, which is formulated as a constrained stochastic simulation optimization problem that consists of a huge input-variable space formed by the vector of threshold values in the testing process. First, we construct a crude but effective...
Due to the escalating costs associated with testing of precision RF components, there is a pressing need for identifying novel test methods that allow RF circuits to be tested with low cost test instrumentation. Specifically, test costs can be lowered significantly if stimulus from a digital pattern generator can be adapted to serve as test stimulus for analog/RF circuits. In this paper, we propose...
Standard methods to quantify SER susceptibility in memory devices have been established during 2000-2008. JESD89A issued in 2006 covers a wide variety of test methods for terrestrial neutrons and alpha particles. Spallation and (quasi-) monoenergetic neutron tests are among the best options for the SER tests. The methods, however, are being recognized as getting more inaccurate as device scaling proceeds...
Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSV) promise high-performance low-power functionality in a smaller form factor at lower cost. Stacking entire wafers has attractive benefits, but unfortunately suffers from low compound stack yield, as one cannot prevent to stack a bad die to a good die or vice versa. Matching individual wafers from repositories of pre-tested wafers...
Recent advances in the semiconductor industry enable the integration of many processing units on a single die and new processors are often included into large many-core SoCs. The dependability of such a many-core processor is essential for many mission-critical applications. Ideas such as the Know-Good-Tile concept [1] or majority-voting among tiles [2] have been proposed to explore the possibility...
This paper describes the development of adaptive test in response to the ever growing need to dynamically and cost effectively tailor IC testing to discriminately manage manufacturing process variations. Various degrees of adoption are presented, together with benefits and examples of it's use. Finally, challenges for future development are discussed.
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D stacked ICs implemented using Through-Silicon Vias (TSVs) technology. We consider 3D-SICs with both fixed given and yet-to-be-designed test architectures on each die and show that both corresponding problem variants are NP-hard...
In a scan-based test architecture, the scan power and and test data volume can be reduced by utilizing a double tree scan (DTS) architecture. This paper presents a novel hardware implementation of the DTS architecture and compares the hardware overhead with the conventional scan architecture. The implementation proposed utilizes a clock structure which greatly decreases the number of clocked flip-flops...
We present a Linear Feedback Shift Register (LFSR) like architecture, because the LFSR can bring a lot of data by using a few bits. We calculate the ATE data by Gauss-Elimination and put the ATE data to our decompression architecture to generate a lot of patterns. And one ATE data will run several times in the architecture. If some faults cannot be detected, we will generate the patterns which are...
At-speed testing is essential for VLSI ICs implemented in nanometer technologies, operating at high clock speeds. Traditional scan based methodologies can be used for at-speed testing using a transition delay fault model. There are two common techniques to launch the transition-launch-on-shift (LOS) and launch-on-capture (LOC). LOS gives better fault coverage than LOC, but the main drawback of LOS...
We propose a method to analysis the delay of the sub-path on fabricated chips by the several path-delay tests. In recent years, the process variation causes the timing faults. To detect the faults, the path-delay test is one of the most promising methods. The path-delay test checks whether the signals along the target paths in fabricated LSIs are propagated under the specified frequency. In this paper,...
This paper reports the derivation of the Cramér-Rao lower bound for the estimation of the code transition levels of an analog-to-digital converter (ADC) and of the output levels of a digital-to-analog converter (DAC). Numerical results for the estimation of the integral nonlinearity are given. The converters are tested by sampling many times, with the ADC, each dithered output level of the DAC. The...
In the context of SRAM testing, we propose a methodology to define proper conditions under which SRAMs should be tested to improve their reliability. This methodology is especially suitable to deal with the impact of threshold voltage variability affecting SRAM core-cell transistors. By establishing an objective manner of comparing different test conditions, the proposed study shows how it is possible...
An experimental study of transient latchup is conducted. Measurements are performed on test structures fabricated in 90-nm and 130-nm CMOS technologies. The worst case testing conditions differ for static and transient latchup. Device simulation is used to understand the measurement results. P-well and N-well guard rings are evaluated under transient test conditions.
The aim of the work is ultimately to establish a theoretical foundation for economical decision making on whether to test; how far to test; whether testing is feasible; and, otherwise, whether there is an alternative to defect tolerance with little or no testing. In this work, a new defect tolerance for the circuits and systems under the circumstances where little or no testing is allowed or feasible,...
At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investigated in the literature in the last few years, especially regarding test power consumption. Conversely, LOS has received much less attention. In this...
When testing resources are severely limited, special attention must be paid to critical faults so that important or frequent field failures arising from test escapes can be minimized. We present a new algorithm to optimize test sets that considers the criticality of potential undetected defects throughout the testing process and dramatically reduces the criticality of test escapes.
Statistical timing models have been proposed to describe delay variations in very deep sub-micron process technologies, which have increasingly significant influence on circuit performance. Under a statistical timing model, testing of a path can detect potential delay failures caused by different small delay defects. Due to path correlations, the potential delay failures captured by two different...
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