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VLSI design techniques are the key to re-engineering the digital gadgets of any kind which are needed to be operated with lower power to ensure a longer backup time. Power reduction in Arithmetic Logic Unit (ALU) is needed for this requirement. Multipliers and adders are the most important structures which use a larger fraction of power in such arithmetic units. This paper analyses the use of an ancient...
This paper presents a single-path pipelined hardware structure for DFT computation based on the radix-22 FFT algorithm. The proposed structure requires log4N −1 complex multipliers, log2N complex adder/subtracters and 2(N −1) complex data stores. Compared with previously reported single-path pipelined structures, the number of add/subtracters is reduced by 50 percents. A realization of the delay and...
In this paper, a novel systematic design methodology in the category of hybrid-CMOS Logic style is proposed and used for designing full swing balanced Carry-Carrybar circuits. The critical path of the presented designs consists of only one pass-transistor, which causes low propagation delay. High driving capability, full-balanced full-swing outputs and low number of transistors of basic structure...
In this paper, a new computationally efficient compensated prefilter structure is proposed for the design of narrowband lowpass as well as narrowband highpass Finite Impulse Response (FIR) filter. The proposed approach is able to achieve significant savings in hardware in terms of the number of multipliers and adders required when combined with Interpolated Finite Impulse Response (IFIR) technique...
This paper presents an approach for implementing a 8-tap high-performance digital FIR (Finite Impulse Response) filter using Logarithmic Number System(LNS). In the past, FIR filters were implemented by conventional number system; therefore, the speed was limited due to the multiply accumulate operations. We realize a fast FIR filter by utilizing the Logarithmic Number System, which allows simple implementation...
High performance implementation of 2D digital filters are highly desired in many applications for real-time processing. In this paper, a multiprocessor realization of a 2D denominator separable digital filter is implemented in Altera Stratix III FPGA. The implementation achieves a data throughput equivalent to one multiplication and two additions, plus one clock cycle. It has been found that the maximum...
This paper presents a new processor array architecture for scalable radix 8 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architectures extracted by G. Todorov. Moreover, the multiplier bits are fed serially to the first processing...
In a three-dimensional integrated circuit (3D IC) design, through-silicon-vias (TSVs) are used for data transfer across layers. However, TSVs act as obstacles during the stage of placement and routing and have a negative impact on chip yield. Therefore, TSV number minimization is an important topic for 3D IC design. In this paper, we point out that there often exist idle functional units and idle...
All-digital frequency synthesizers are favored by modern nano-scale CMOS technologies but suffer from strong frequency spurs and timing irregularities. This paper reviews the time-domain-correction and spurs-suppression techniques for all-digital frequency synthesizers, identifies their strengths and weaknesses and provides new research directions.
A novel 64-bit hybrid radix-4 sparse-4 tree adder using clock-delayed (CD) footless domino logic is proposed. The adder operates at 6.4GHz with 181ps latency and it consumes 840mW at 1.2V in a standard 90nm CMOS technology. The adder latency is accurately measured by the programmable clock generated from delay-locked loop (DLL). Pseudo-exhaustive testing is applied so that all testable faults in this...
This paper presents an efficient RNS scaling algorithm for the balanced special moduli set {2n−1, 2n, 2n+1}. By exploiting the relationship between the scaling constant and the residues of the three-moduli set using the New Chinese Remainder Theorem I (New CRT-I), the complicated modulo reduction operations for large integer scaling in RNS can be greatly simplified. The scaling constant has been chosen...
De-synchronization is a fast and simple way to design an asynchronous circuit, but it has inherent limitation on performance improvement due to the traditional delay element implementation method. In this paper, a length-variable delay element is introduced to help us design a high performance asynchronous floating-point adder. The completion time can be automatically adjusted depending on the operation...
An area-efficient diminished-1 modulo 2n+1 multiplier with radix-4 modified Booth encoding is proposed. The proposed approach minimizes the number of Booth encoder and Booth decoder blocks required for partial product generation. Its correction factor is decomposed into a multiplier-dependent dynamic bias and a multiplier-independent static bias. The dynamic bias can be generated by hardwiring the...
The research on optimization of Multiple Constant Multiplication (MCM) during the last two decades has been focusing mainly on common subexpression elimination and reduced adder graph algorithms when bit-parallel computation is required. The advancement of FPGA technology enables the implementation of complex MCM instances on FPGA, but the shift-and-add network implementation does not make full use...
Decimal floating point (DFP) arithmetic has been paid more attention in recent years, since it is superior to the binary counterpart in the financial and commercial computing including currency conversion, billing system, banking and tex calculation. Many DFP arithmetic units, such as addition, multiplication, division and fused-multiply-add are not possible to achieve the high performance without...
Energy-efficient serial and parallel multiplier structures are explored to see their suitability in the low and ultra low power design regimes. 16×16-bit serial and state-of-art parallel multipliers are compared in 45nm CMOS. A multiplier structure is proposed by optimizing the architecture, gate sizes and the voltage supply. The proposed structure provides 15% more throughput as compared to two-cycle...
As variable delays are observed in the integrated circuits under different data inputs, it is expected to enhance the performance of the circuit using the average-case design methodology. This paper presents a novel approach using the time-domain multistage speculation to realize a variable-latency circuit, in which speculation points with double-sampling and check-recovery units are inserted into...
We propose a robust asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic (SAPTL) approach with improved speed and power attributes over reported SAPTL approach. These attributes are achieved by simplifying various sub-blocks therein to reduce the stacking of pass transistors and the number of transistor switchings, and to avoid floating nodes. By means of an 8-bit pipeline adder...
A digital bandpass delta-sigma modulator for class-S power amplifiers is presented. In comparison to a 2-level modulator coding efficiency can be increased by 10% over a large input power range with a 3-level modulator. Scaling the quantizer thresholds offers a trade-off between coding efficiency and signal-to-noise ratio. The bandpass modulator architecture allows twofold interleaving. A constraint...
This paper presents a comparative analysis of four different multiplier architectures. The four multipliers include the array multiplier, a bypass multiplier with tree structure, a multiplier with 2-d bypass, and a bypass multiplier using improved column bypassing schemes. The multipliers a reimplemented in 90nm CMOS technology. The architectures are compared in terms of critical path delay, power...
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