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The real-time requirements of hardwired HEVC encoder demand that, at the grain of coding tree unit (CTU), the maximum computation should be reduced by a fast CU mode decision algorithm. In addition, to realize the parallel rate-distortion optimization (RDO) of different CU modes, the current CU mode decision should not use the auxiliary information from other CU modes. Considering the above constraints,...
The IBM TrueNorth (TN) Neurosynaptic System, is a chip multi processor [1] with a tightly coupled processor/memory architecture, that results in energy efficient neurocomputing and it is a significant milestone to over 30 years of neuromorphic engineering! It comprises of 4096 cores each core with 65K of local memory (6T SRAM)-synapses- and 256 arithmetic logic units — neurons-that operate on a unary...
An efficient signaling scheme for serial-data transceivers (TRXs) has been proposed, which can properly reduce inter-symbol interference (ISI) and crosstalk (Xtalk) in memory interfaces. The proposed architecture relies on fully-digital implementation rather than analog/multi-tone approach, which can offer a very power-efficient and versatile silicon implementation. Moreover, the Xtalk induced noise...
This paper presents a hardware design for the Fractional Motion Estimation (FME) of the High Efficiency Video Coding (HEVC) standard. The solution designed in this work uses a scheme to reduce the number of accesses to the reference frames stored in the external memory in up to 49.22%. A strategy to reduce the computational effort is also used. This strategy consists in using only the four square-shaped...
Memory-based computing using associative memory has emerged as a promising solution to reduce the energy consumption of important classes of streaming applications such as multimedia by avoiding redundant computations. In associative memory, a set of frequent patterns that represent basic functions are pre-stored in ternary content addressable memory (TCAM) and reused. The primary limitation to using...
High speed multiplier designs have been the primacy for multiplier dominated applications such as wireless communications, computer applications, and image processing. In this paper a high performance fixed word length multiplier design by using recently proposed technique to eliminate the error correcting word and a delay efficient parallel prefix Ling adder for final redundant binary to normal binary...
In this paper, Radix-4 Modified Booth Encoding (MBE) is used to generate partial product. The proposed 32-bit multiplier is based on pipelining. The main target is to reduce the delay of higher bits multiplier and speeding up the computation. The proposed design is implemented in Xilinx 14.2. The delay achieved is 2.826ns for computing 32×32 bit signed multiplication with maximum frequency of 353...
Various physical layer protocols are employed to encode information bits in short range wireless communication technologies. In this paper, we propose a multimode hardware architecture for a digital baseband encoder which incorporates Manchester, Differential Manchester and FM0 codes. These codes help in achieving good DC balance thereby improving signal reliability. Alternating Manchester with Differential...
On-line machine learning has become the need for future data analytics. This work will show an RRAM-crossbar based l2-norm hardware solver for on-line machine learning that can significantly reduce training time when compared to the traditional gradient-based solution using backward propagation. Intensive matrix-vector multiplication in l2-norm solution can be mapped onto recent resistive switching...
This paper presents an implementation of a communications stack for underwater communications and relative localisation. The application scenario, under the auspices of the EC MORPH project, is described. The high-level architecture is described, with the relevant hardware and software implementation details. A summary of the localisation methods, based on previous works, is given, followed by a discussion...
The main reason for the long time and high energy requirements of state-of-the-art Video Coding (VC) standards, such as the HEVC, is the large amount of distortion calculations. Among the most known and used ones is the Sum of Squared Differences (SSD) which has a strong correlation with the Peak Signal-to-Noise Ratio (PSNR). Such correlation is explored by current encoders to provide a good trade-off...
In this paper, a novel attempt is made to design a reconfigurable coder system which can be reconfigured on-the-fly to work either as an encoder, or decoder, or both encoder and decoder depending on the user requirements. In order to build the proposed reconfigurable system, Convolutional encoder, Viterbi decoder, Golay encoder and Golay decoder are employed in different combinations for the proposed...
In Cloud-based VDI, users can access the virtual desktop service anytime and anywhere with the wide variety of terminals. The lightweight virtual desktop display protocol is required to support more users on the limited resources and to provide service to mobile users. In this paper, we design and implement the virtual desktop system using lightweight virtual desktop display protocol which would reduce...
High-level synthesis (HLS) promises high-quality hardware with minimal development effort. In this paper, we evaluate the current state-of-the-art in HLS and design techniques based on software references and architecture references. We present a software reference study developing a JPEG encoder from pre-existing software, and an architecture reference study developing an AES block encryption module...
We present the design and organization of an homogeneous asynchronous bit-level array based on Null Convention Logic. A bit element (bel) array represents a bit-level hybrid processor that exhibits both Spatial and Temporal computing characteristics. The bit elements are organized in a 2D grid, with eight-way connectivity. Programs represented as Directed Acyclic Graphs can be mapped to the array...
We propose a technique for optimizing the High Efficiency Video Coding (HEVC) encoder by reducing the number of operations performed in the motion estimation stage. The technique is based on the fact that a significant number of motion estimation operations are performed repetitively for the same image samples, but for different block partition sizes. By decoupling the initial motion estimation and...
This paper proposes a hardware architecture for the newly introduced Better Portable Graphics (BPG) compression algorithm. Since its introduction in 1987, the Joint Photographic Experts Group (JPEG) graphics format has been the de facto choice for image compression. However, the new compression technique BPG outperforms JPEG in terms of compression quality and size of the compressed file. The objective...
Since the rapid development of post-CMOS technologies in the last decade, there has been a growing interest in utilizing them for implementing neuromorphic or brain-like computing machines. Besides attempts to build realistic circuits that would mimic the functioning of biological neurons as close as possible [1][2], our team is focused on implementing neuromorphic circuits suitable for embedded applications...
In this paper we are going to study Array multiplier, Wallace multiplier, Bypassing multiplier, Modified Booth multiplier, Vedic multiplier and Booth recorded Wallace tree multiplier which have been proposed by different researchers. When the study of the various multipliers have been performed, Array multiplier is found to have the largest delay and large power consumption while Booth encoded Wallace...
This paper proposes fault tolerant Network on Chip (NoC) architecture which enables switching of error control coding scheme present in data link layer and network layer as needed, depending upon the rate of error at runtime. The proposed Joint Crosstalk Avoidance-Five Bit Error Correction-Six Bit Error Detection (JCA-FBEC-SBED) error control coding scheme is used in both the layers. This scheme provides...
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