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The multilevel inverter technology has gained a tremendous significance in the research area. This paper proposed a new controller for generating the switching sequence of power devices used in multilevel inverter to produce the desired output. An embedded code has been developed to control the switching states of different IGBT switches. To validate the effectiveness of the proposed technique to...
Many digital Signal processing (DSP) applications requires complex arithmetic operation which is carried by multiplier and adder units. Multiplication operation can be done as a successive addition which introduces delay in the processing. In which implementation of this technique with delay constraints leads to more challenging. Because the internal modules generate delay in propagation of processed...
In this short paper, we propose a hybrid TCP PEP combined XOR coding with TCP Hybla on split PEP in satellite communication. To evaluate performance of the proposed protocol we set up a test bed of satellite communication network. As a result of performance evaluation of the proposed Hybrid TCP on split PEP, the file transmission speed improved more than 40% in high error rate environment. Therefore,...
In this paper, we propose a low complexity algorithm to separate collided RFID signals. By carefully analyzing the collided signals when two tags with the same bit durations respond to a reader simultaneously, we observed that the individual amplitudes of each tag appear in pairs and the two tags' information bits are different, and regular RFID signals with larger amplitudes appear if the two tags'...
As the physical limits of Moore's law are being reached, a research effort is launched to achieve further performance improvements by exploring computation paradigms departing from standard approaches. The BAMBI project (Bottom-up Approaches to Machines dedicated to Bayesian Inference) aims at developing hardware dedicated to probabilistic computation, which extends logic computation realised by boolean...
The detection of molecular markers such as micro ribonucleic acid (miRNA) expression levels in the cells are essential for diagnosis of a disease, especially cancer. Recently, a huge amount of molecular markers on cell is being extracted by single molecular detection method, as results, excessively detection process and time is required. Meanwhile DNA computing has capabilities to interact with biological...
We realized an all-optical digital physical-layer network coding in Fiber-Wireless networks by employing two SOA-MZI XOR gates. Encoding and decoding operations are demonstrated for 1Gb/s data on 10GHz subcarrier and extended to 60GHz with simulations.
Since the introduction of Private Circuits at CRYPTO 2003, several works have attempted its implementation in hardware. Only very recently was an implementation of this masking scheme shown to survive state-of-the-art leakage detection tests. The overhead introduced to achieve the provable security was significant. Similarly, the implementational aspect of Private Circuits II, the tamper-resistant...
Aiming at issues of load imbalance and low energy efficiency in the existing underwater sensor network clustering algorithm, a novel global optimal clustering algorithm with the low complexity and parallel processing is proposed. The algorithm is based on the basic idea of particle swarm optimization algorithm (PSO). After the binary initial code of the sensor nodes, the particle code is adjusted...
Reversible logic has gained significant prominence in recent years due to its wide spread application in quantum computing. The major advantage of reversible logic circuit over conventional logic circuits is reduced heat losses during computation. Comparators are widely used in digital communication devices, encryption devices, sorting networks, data converters, address decoding circuitry in computers...
Communicating data from sensors such as gyroscopes and accelerometers, to processors, typically occurs over printed circuit board traces. This communication can cost up to 40 µW at data rates of 1 Mb/s.
Solutions that allow the computation of arbitrary operations over data securely in the cloud are currently impractical. The holy grail of cryptography, fully homomorphic encryption, still requires minutes to compute a single operation. In order to provide a practical solution, this paper proposes taking a different approach to the problem of securely processing data. FRagmenting Individual Bits (FRIBs),...
In this paper, we propose a counterexample-guided diagnosis approach to identify faults in circuit designs described as net-lists on the gate-level. Given a faulty net-list and a logic specification of the correct, intended behavior of the circuit, the diagnosis algorithm iteratively computes the exact set of fault candidates, i.e., a subset of the circuit's gates at which all counterexamples can...
The paper describes a method of verifying sequential arithmetic circuits by adding a special type of redundancy, called "Vanishing Polynomials" and "Don't Care Polynomials". The proof of functional correctness consists in transforming the polynomial expression at the primary outputs into a unique polynomial in the primary inputs and comparing the computed...
In this paper, a new method for the construction of a quantum stabilizer code from circulant permutation matrices is discussed. First, we choose a finite-length vector randomly, and we can construct circulant permutation matrices from the vectors. Then, the parity-check matrix can be produce from the circulant permutation matrices. Hence, the generators of stabilizer code are determined according...
This paper proposes an area-efficient partial-sum generator (PSG) architecture for polar decoder implementation. High-throughput PSG designs mainly consist of an encoding matrix generator and a partial-sum update circuit. The matrix generator conventionally is built by cascading a series of D flip-flops and XOR gates. By decomposing the target matrix into the Kronecker product of smaller matrices,...
LDPC decoders on faulty hardware have received increasing attention over the last few years, mainly motivated by reliability issues in emerging nanotechnologies. As a main result, it was shown that LDPC decoders are naturally robust to hardware faults. LDPC encoders on faulty hardware have received less attention, and they are expected to be less robust to hardware faults. In this work, we propose...
The versatility and cost of embedded systems have made it ubiquitous. Such wide-application exposes an embedded system to a variety of physical threats like side-channel attacks (SCA) and fault attacks (FA). Recently, a couple of software encoding schemes were proposed as a protection against SCA. These protection schemes are based on dual-rail precharge logic (DPL), previously shown resistant to...
Single clock distribution over a large high performance chip can be very challenging. This led to evolution of globally asynchronous and locally Synchronous (GALS) systems in modern deep sub-micron (DSM) technology. In GALS mostly bundled data protocols which are based on handshake mechanism, are used for data transfer. But these protocols rely on timing assumptions between handshake signals and data...
Approximate or inexact computing has recently attracted considerable attention due to its potential advantages with respect to high performance and low power consumption. This paper presents the design of an approximate multiplier; this approximate multiplier consists of an approximate Booth encoder, an approximate 4-2 compressor and an approximate tree structure. The approximate design is implemented...
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