The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Traps that are located in the gate oxide of MOSFETs have been established as a cause of low-frequency noise phenomena. Analysis of such noise is usually based on frequency domain, stationary models. It has been shown that such simplistic models produce erroneous results for circuits with time-varying bias conditions. Tian <etal/> proposed an idealized trap model with the goal of capturing the...
The potential application of Defected Ground Structure (DGS) for isolation improvement of series discrete PIN diode switch is proposed in this paper. A square dumbbell DGS was selected for this application where it was connected in parallel with a single series discrete PIN diode. By realizing the circuit using FR4 substrate, the simulated and measured result clearly show that the isolation of the...
As technology scales into the nanometer regime ground bounce noise and noise immunity are becoming important metric of comparable importance to leakage current, active power, delay and area for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cells are proposed for mobile applications with low ground bounce noise and a novel technique has been...
This paper presents a Ka-band high isolation single-pole-double-throw (SPDT) switch using 0.13μm CMOS process. The switch has a measured insertion loss of 2.7–3.7 dB and an input 1-dB compression power (P1dB) of 8 dBm at 35 GHz. Via using the shunt NMOS topology and high quality factor match networks, 33–50 dB measured isolation is obtained within the frequency range of 30–45GHz. The switch core occupies...
Gate-level timing simulation of combinational CMOS circuits is the foundation of a whole array of important EDA tools such as timing analysis and power-estimation, but the demand for higher simulation accuracy drastically increases the runtime complexity of the algorithms. Data-parallel accelerators such as Graphics Processing Units (GPUs) provide vast amounts of computing performance to tackle this...
Distributed Power System (DPS) is a widely adopted power structure for renewable energy application and tele-communication, computer system, aerospace industry, etc. DPS is more reliable and flexible than the traditional concentrated power system. The communication for the DPS utilities plays an important role in the system framework. The reliability, low cost and easy implementation are important...
We propose a fast and precise simulation method for replicating the transient responses and frequency characteristics of switching power converters using a mixture of real circuits and behavioral models. The method used a behavioral simulation tool (Verilog-A), which was supported by an analog simulator such as SPECTRE®. The time-step became variable, however, the nonlinear operation of the circuit...
This paper studies the influence of different implementation methods of a simple control algorithm over the chaotic behavior of a specified circuit. Two new methods are presented: one is using a microcontroller and the other is using logical gates. The article also presents a unique approach to modelling a negative resistance as simple as possible, closely resembling a proposed mathematical dependency.
This paper proposes a novel switching strategy for high efficiency of a single-phase three-level inverter. Normally, the conventional unipolar and bipolar switching methods are used in the single-phase three-level inverter. In comparison with two conventional switching methods, the proposed switching method, which keeps switching state of some switches for switching period, is advantageous in efficiency...
Gate-level power estimation based on foundry-supplied standard cell libraries is a common analysis step during digital design. Surprisingly little is known about the accuracy of this approach and the suitability for different circuit types. At the same time, commercial tools implementing this approach are employed broadly and often regarded as the reference when comparing estimation methodologies...
Simulation techniques cannot cope with the distributive and reactive nature of Network on chip (NoC) architectures very well and thus compromise on the accuracy of the analysis results. Formal verification has been used to overcome these challenges but, to the best of our knowledge, has been mainly used for the verification of packet-switched NoC's. The main focus of this paper is on the formal verification...
Electric Vehicle (EV) and Hybrid EV (HEV) require higher voltage than what a single storage cell can output, so a large number of cells are needed to be connected in series. For the series connected storage cells, the voltage equalizer is required. In this paper, modularized LC resonant switched capacitor cell voltage equalizer is proposed. By means of modularizing and Zero Current Switching (ZCS),...
This paper presents the concept of a switching loop snubber that suppresses the device's parasitic ringing by inserting a damping loop that is closely coupled with the original switching loop. The proposed snubber circuit damps only the high-frequency oscillations during the switching transients without either lowering the switching speed or increasing the conduction loss. The operation principle...
We present a physical circuit model for polarization reversal dynamics in ferroelectrics, which is implemented in Verilog-A, validated with PZT measurements and applicable in all operation modes for bulk, epitaxial and polycrystalline thin films. Consistent treatment of field-driven polarization not only gives accurate step-voltage responses across many decades in time, but also reproduces frequency...
Presented here is experimental and simulated demonstration of a 96% efficient GaN based synchronous boost converter switching at 1 MHz. First, experimental implementation of the GaN based boost converter with 96% efficiency is established. A behavioral model of the GaN transistor is then developed in Saber, by reproducing five experimentally measured DC characteristics. The GaN device model is subsequently...
A new method for modeling switched-linear systems is presented: switching devices are modeled ideally using parametrized curves, and an efficient implementation for real-time simulation is proposed. Experiments on a rectifier topology for traction converters demonstrate the methods performance in terms of accuracy, stability and execution time, with a 50us step-size.
An enhanced circuit model is developed for a 60-GHz single-pole single-throw (SPST) switch in 65nm CMOS technology in this paper. The enhanced circuit model involves the modeling of the drain-to-source parasitic capacitances that are introduced by the overlapped multi-finger drain-to-source metallization of the transistors and also the modeling the distributive and coupling effect of lines interconnection,...
The massive big data transfer requirements in the cloud age are posing unprecedented challenges on todays' network infrastructure. Delivering data in a cost effective and scalable manner is of critical importance to support the continued growth of cloud services. In this paper, we revisit the problem of delivering large data on top of dynamic circuit switched networks, with a particular focus on how...
Passive nano-crossbars arrays are highly attractive structures which enable ultra dense non-volatile memories, novel logic-in-memory approaches, and efficient synaptic connections for neuromorphic computing approaches. The basic junction element is a memristive element, i.e. a non-volatile two terminal resistively switching device. In conjunction with a select device paradigm large-scale arrays are...
The purpose of reconfiguration process in PV systems is to find the connection structure of the highest amount of power obtained by the system under partial shading conditions. In this paper, a new genetic-algorithm based approach was presented for the reconfiguration. The system tries to maximize the obtained power in the same sub-module combining the ones that have the most approximate radiation...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.