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As the number of processing elements which can be placed on a single chip doubles about every two years, both System-on-Chip (SoC) and the microprocessor market call for high-performance, flexible, scalable, and design-friendly interconnection network architectures [1]. Network-on-Chip (NoC) has been proposed as a solution to multi-core communication problems. The advantages of NoC include high bandwidth,...
This paper proposes a novel relay selection protocol for distributed cooperative networks, that eliminates the effect of asynchronism between different received signals. The suggested protocol maintains a high diversity order, with minimum message complexity and overall time delay, and it also provides a better performance in terms of power consumption and error rates than existing selection protocols...
This paper presents a new approach of using the improved hybrid LUT-based architecture for the low-error and efficient fixed-width squarer circuits. By employing both LUT-based and simple conventional logic circuits, the good trade-off between hardware complexity and performance can be achieved. Moreover, the mathematical identity of squaring operation is exploited so that the error can be reduced...
Future Internet research activities try to increase the flexibility of the Internet. A well known approach in this area is to build protocol graphs by connecting functional blocks together. The protocol graph that should be used is the one most suitable to the application's requirements. This paper presents a Multistep Process Model to find the most suitable protocol graph. We evaluate our proposed...
In Orthogonal Frequency Division Multiplexing and Discrete Multitone transceivers, a guard interval called Cyclic Prefix (CP) is inserted to avoid inter-symbol interference. The length of the CP is usually greater than the impulse response of the channel resulting in a loss of useful data carriers. In order to avoid long CP, a time domain equalizer is used to shorten the channel. In this paper, we...
Wireless mesh networks (WMNs) have been increasingly used to carry multimedia traffic with flow requirements. The performance of multi-radio multi-channel (MRMC) WMNs largely depends on the routing and channel assignment. Because routing and channel decisions are coupled, they need to be jointly optimized to achieve the best performance. This is the so-called routing and channel assignment (RCA) problem,...
Real-time systems are often modeled as a collection of tasks, describing the structure of the processor's workload. In the literature, task-models of different expressiveness have been developed, ranging from the traditional periodic task model to highly expressive graph-based models. For dynamic priority schedulers, it has been shown that the schedulability problem can be solved efficiently, even...
One of the possible solutions is to use space division multiplexing in order to overcome the capacity crunch. Few mode fibers (FMF) have attracted a lot of attention in the recent years, however still a lot of research is required to enable transmission over FMF. One of the problems with the realization of FMF transmission is that these fibers have a modal dispersion which results in high number of...
We address the problem of finding the least cost disjoint path pair with delay constraints, where working and protection paths require different delay constraints. A heuristic algorithm is proposed and compared with optimal ILP results.
As system sizes grow and devices become more sensitive to faults, adder protection may be necessary to achieve system error-rate bounds. This study investigates a novel fault detection scheme for fast adders, long residue checking (LRC), which has substantive advantages over all previous separable approaches. Long residues are found to provide a ~10% reduction in complexity and ~25% reduction in power...
This study proposes an energy detection based time synchronization scheme for IR-UWB systems. The proposed synchronization scheme may achieve symbol timing synchronization within a symbol interval. The mean square error (MSE) performance of the proposed scheme is compared with that of the TDLC algorithm, in both residential line-of-sight (LOS) and non-line-of-sight (NLOS) propagation environments...
In the near future, embedded systems containing hundreds of processing elements running multiple concurrent applications will become a reality. The heterogeneous multicluster architecture enables to cope with the challenging hardware/software requirements presented by such systems. This paper shows principles and optimization of multicluster dimensioning aiming at an appropriate distribution of applications...
For the first time, a full platform using FDSOI technology is presented. This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology. We show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values. Yield of ∼14Mb SRAM cells is demonstrated, allowing to measure...
In this present work, we propose a scheduling approch for heterougeneous traffic over network. The proposed scheduling not only satiesfies the QoS requirements of the real time flows (class-1) but also continues providing best effort service to non real time flows (class-2). Many scheduling techniques have been proposed to respond to the temporal requirements of real-time jobs (flows). The technique...
This paper presents a novel approach to perform modular arithmetic addition and subtraction using base-1 thermometer code data format for operands corresponding to the residues of the same modulus. Two n-bit thermometer code operands are first concatenated and logically shifted to produce a normalized 2n-bit thermometer code intermediate sum. Modulo operation is then applied to this 2n-bit intermediate...
This paper introduces reconfigurable two-stage finite-length impulse response (FIR) Nyquist filters. In both stages, the Farrow structure realizes reconfigurable lowpass linear-phase FIR Nyquist filters. By adjusting the variable multipliers of the Farrow structure, various FIR Nyquist filters and integer interpolation/decimation structures are obtained, online. However, the filter design problem...
This paper introduces a new class of linear-phase Nyquist (Mth-band) FIR interpolators and decimators based on tree structures. Through design examples, it is shown that the proposed converter structures have a substantially lower computational complexity than the conventional single-stage converter structures. The complexity is comparable to that of multi-stage Nyquist converters, although the proposed...
Systolic structures for finite field multiplication involve large number of registers for parallel implementation, while bit-serial implementations require a large computation time, which increases along with the order of the field. In this paper, we present a novel scheme for the decomposition of the multiplication over GF(2m) based on irreducible trinomials into several independent units that facilitates...
This paper proposes a class of downsampled floating tap decision feedback equalization (DFE) architectures based on downsampling of the floating tap positions. The architectures offer significant complexity and power reduction compared with a standard floating tap DFE architecture with minimal loss in performance. Simulation results with realistic channel models are used to validate the performance...
Wireless ad hoc networks suffer from several limitations, such as routing failures, potentially excessive bandwidth requirements, computational constraints and limited storage capability. Their routing strategy plays a significant role in determining the overall performance of the multi-hop network. However, in conventional network design only one of the desired routing-related objectives is optimized,...
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