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Non-linear solar photovoltaic (SPV) system characteristics and its dependency on meteorological variables of irradiance and temperature; renders this energy source rather involved to visualize. In this paper a low power realtime SPV module simulator is realized in field programmable gate array (FPGA) XCS100E platform for classroom teaching. FPGA platform is used due to its parallel computing nature...
With the teaching experiment reform of computer science, designing CPU with HDL (Hardware Description Language) as a curriculum experiment becomes more and more extensive. In the meantime, many problems also follow. In order to solve the problems in the process of designing MIPS CPU with HDL, in this paper, we propose a MIPS CPU test system for practice teaching, which simplify the test process in...
At present, with the reform of teaching experiments of computer science in colleges and universities, many colleges and universities have designed a variety of experiment teaching courses for students. In our university, we set up experiment teaching courses based on FPGA (Field — Programmable Gate Array) development board for students in both digital logic and computer organization courses. Aiming...
Digital Logic course and Computer Composition Principle course are important professional basic courses of computer major. In the traditional teaching mode, the experiments of these two hardware courses are mainly implemented to validate the theoretical knowledge by plugging wires in different experiment boxes, which leads to a lack of computer system design and development capability of computer...
In this paper, we have presented a design of hybrid arithmetic logic unit (ALU) in Double precision format (DPF) according to the IEEE-754 standard. In this we have designed an ALU which consists of the two different architectures. First architecture is semi-floating point unit (Semi-FPU) and the second architecture is floating point unit (FPU). Semi-FPU takes a 32-bit integer input and produces an...
Modern day system-on-chip (SoC) designs have many inbuilt IP cores and it is crucial that the communication between these cores is properly synchronized. This synchronization is ensured by the interconnects based on various bus protocols. Hence, it is crucial to verify these interconnects during the development of such SoCs and this is what takes most of the time as compared to the design stage. But...
This article discusses the implementation of a wide band vectorial digital modulator and a tool to evaluate the Bit Error Rate. This modulator is capable of generate a wide band (up to 6.3 MHz) 16-QAM modulation in baseband. A second functionality programmed in the tool and reported in this article evaluates the Bit Error rate in order to measure the received signal quality. Results are validated...
System-on-a-Chip (Soc) design has become more complex, because many functional components or IPs (Intellectual Property) will be integrated within a chip. The test of integration is “how to verify on-chip communication properties”. Since conventional simulation-based bus protocol monitors can validate whether bus signals obey bus protocol or not, but they often lack of efficient debugging techniques...
In this paper, a Verilog-AMS based methodology for automated verification is discussed. This solution is geared towards aiding the verification of behavioral models, which designers are tasked with when developing or editing a schematic. Up to now the conventional way to verify the operation of a model and how much it mimics the operation of a schematic is to visually inspect the output signals between...
We present the first Verilog-A based models of a magneto-electric magnetic tunnel junction (ME-MTJ) based XNOR and NOR logic gates. The ME-MTJ is a low-power beyond-CMOS technology, with possible applications in memory and logic devices. The models presented here have been developed in Verilog-A and validated with simulations using cadence spectre. We show the operation of this ME-MTJ dual-purpose...
Array Signal Processor is a complex ASIC which can perform Phased array beam forming of Ultrasound Sensor data up to 32 channels. The Array Signal Processor consists of Transmit Beam Former, Transducer, and Receive Former. The Array signal Processor works based on the principle of Pulse-echo Processing. When the voltage is applied to the transducer probe, pulses are produced due to piezoelectric effect...
Electronic circuits design is extremely important in information processing or communication systems. Classical design method of electronic circuit is manual programming. The cost of design and test is usually expensive, especially for large scale or complicated circuits. In this paper, hardware circuit is designed by formal method. Behavior of the circuit is described by multiple extended hierarchical...
In the recent days Fast Adders are implemented to increase speed, reduce delay, besides being cost effective. Several architectures and implementations of binary adders, gates, etc. were used in the past. But it was leading to complexity of the structure and also obscurity in implementation. In the proposed research paper implementation of Carry Look-ahead Adder (CLA) using Fast Adder for signal processing...
This paper investigates the networked control for a class of switched systems under asynchronous switching. The asynchronous switching phenomenon, which means that the switching time of the matched controller mode usually lags behind that of the switched system mode, is caused by network-induced imperfections. To deal with the coupling between the switching interval of switched systems and the execution...
Life cycle management is an effective way to maintain software quality in safety-critical systems; however, it faces difficulties when applied on software of Programmable Logic Device (PLD). This is because: (1) traditional models on software development do not fit with design workflow of PLD; (2) adaptive models for PLD focus mainly on specific features during software implementation, ignoring high-level...
With the invention of IoT, the image processing is reaching upto a distinct level as IoT is becoming a major part of every one life. These systems are creating many applications in image processing field such as image filtering and processing. The realization of this system was completed by means of a low cost ZedBoard Zynq 7000 FPGA and a Raspberry-pi. The output for the input image after processing...
Sensor selection in control design receives substantial interest in the last few years. We disseminate work on Field Programmable Gate Array (FPGA)-based embedded software platform validating a systematic sensor selection framework and target efficient FPGA resource allocation. Sensor selection combines multi-objective optimization, Linear-Quadratic-Gaussian (LQG) control, applied to a Maglev suspension...
The Red Pitaya [1] is an affordable (< 250 Euros) field-programmable gate array (FPGA) board with fast analog inputs and outputs (sampled at 125 MHz). This makes it useful for quantum optics experiments, in particular as a digital feedback controller for analog systems. Based on the open source software provided by the board manufacturer, we have created the software package PyRPL [2] (Python RedPitaya...
High-Level Synthesis (HLS) is more and more becoming an important part of the digital logic design flow. Rapid development of hardware offloading designs implemented in FPGA accelerators or in the programmable logic area of modern SoC FPGAs is facilitated by the ability of today’s HLS tools to generate logic from generic programming languages such as C and C++. When such accelerators are used in applications...
This study presents the application of the commercial High Level Synthesis (HLS) to a hardwired control application with quantitative comparison to the traditional approach that uses logic synthesis with HDL. Though the derived circuits from HLS are comparable to that of logic synthesis, the design trade-offs in HLS are difficult to control. This study also presents the design and evaluation of the...
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