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Heterogeneous computing with hardware accelerators is a promising direction to overcome the power and performance walls in traditional computing systems. CPU-accelerator integrated architectures, such as CPU with ASIC or FPGA based accelerators, are able to provide customized processing according to application requirements and are thus particularly attractive to speed up computation-intensive applications...
We introduce PyRTL, a Python embedded hardware design language that helps concisely and precisely describe digital hardware structures. Rather than attempt to infer a good design via HLS, PyRTL provides a wrapper over a well-defined "core" set of primitives in a way that empowers digital hardware design teaching and research. The proposed system takes advantage of the programming language...
In this work, we propose for the first time a Verilog-A physics-based compact model of Random Telegraph Noise (RTN) in Resistive Random Access Memory (RRAM) devices. Starting from the physics of the RTN mechanism in both high (HRS) and low (LRS) resistive states, and combining experimental data with physics-based simulations, we develop and validate a complete compact model of RTN in RRAM devices...
In recent years, synthetic test instruments have become increasingly popular in the automatic test equipment (ATE) market. This type of instrument gives users the ability to create custom solutions to better meet their test requirements. FPGA (Field Programmable Gate Array) based solutions are the most common synthetic test instrument on the market today. FPGA based solutions can work well due to...
Today's dominant hardware description languages (HDLs), namely Verilog and VHDL, tightly couple design functionality with timing requirements and target device constraints. As hardware designs and device architectures became increasingly more complex, these dominant HDLs yield verbose and unportable code. To raise the level of abstraction, several high-level synthesis (HLS) tools were introduced,...
The P4 language provides a way to describe a custom network packet processing behavior that involves header parsing, matching and assembling modified packets. Such abstraction represents a significant step towards removing the limitation of fixed-function networking devices. Our live demonstration shows a straightforward usage of an algorithm and tool that maps a P4 program to a general architecture...
This paper proposes a hardware accelerator for n-dimensional (nD) FastICA methodology, introducing the concept of Vector Cross Product into the Coordinate Rotation Digital Computer (CORDIC) based FastICA to attain high computation speed. The complete FastICA Iteration stage required for computation of the nth weight vector is eliminated by using Vector Cross Product in nD FastICA. Introducing Vector...
In this contribution, we present a coverage driven functional verification environment based on the UVM framework and the System Verilog language to certify the operational correctness of the ECC error management logic used in volatile and nonvolatile memories. We apply this methodology to floatinggate nonvolatile memories for the embedded market, which requires a read error rate of 10−14. The proposed...
Increased complexity of computer hardware makes close to impossible to rely on hand-coding at the-level of HDLs for digital hardware design. High-level synthesis can be employed instead, in order to automatically obtain HDL codes from highlevel language functional descriptions. With high-level synthesis it becomes easier to design coprocessors, accelerators, and other special-purpose hardware. Nonetheless,...
Open source hardware projects are becoming more and more common. OpenRISC SOC, one of the prominent of these projects, has become quite popular with the support of volunteer developers. In this work, we have demonstrated the design of an DES (Data Encryption Standard) based system, that can be used in security applications, on ORPSoC-v2 (Openrisc Reference Platform System-on-Chip). Additionally, we...
This paper presents the Verilog-A implementation of charge control based model of dual gated graphene field effect transistor (GFET) and initial results towards bending induced changes in their electrical response. The ambipolar region of the device has been described using the saturation and displacement current models. The output characteristics derived from Verilog — A simulation is in good agreement...
BER (bit error rate) measurement is an important criterion to analyze digital communication systems. In literature this measurement generally performed through simulation programs like Matlab/Simulink. It is considered that the simulation programs may not represent a real communication system and also they are quite time consuming and expensive. However, modeling communication systems with parallel...
FPGAs have emerged as a cost-effective accelerator alternative in clouds and clusters. Programmability remains a challenge, however, with OpenCL being generally recognized as a likely part of the solution. In this work we seek to advance the use of OpenCL for HPC on FPGAs in two ways. The first is by examining a core HPC application, Molecular Dynamics. The second is by examining a fundamental design...
The magneto-electric magnetic tunnel junction (ME-MTJ) is a voltage controlled beyond CMOS device based on the principle of ME anti-ferromagnetic (AFM) exchange biasing of chromia (Cr2O3) and the tunneling magnetoresistance (TMR) of a magnetic tunnel junction (fixed/free ferromagnet (FM) stack). These devices have previously been demonstrated for the implementation of digital logic and memory applications...
Managing the power in highly-integrated systems on chips becomes inevitable in modern designs. Complex systems require complex power management, and it is always difficult to determine whether the designed power management is the most efficient. In our previous work, we have proposed a simplified power-management specification method at the system level of abstraction. In this paper, we propose a...
In this paper, we describe a Selectable Grained Reconfigurable Architecture (SGRA) in which each Configurable Logic Block can be configured to operate in either fine-grained or coarse-grained mode. Compared with the Mixed Grained Reconfigurable Architecture (MGRA), which has a fixed ratio of fine- and coarse-grained operation blocks and a heterogeneous floorplan, SGRA offers greater flexibility in...
This article shares experience and lessons learned in teaching course on programmable logic design at Universitas Muhammadiyah Surakarta, Indonesia. This course is part of bachelor of engineering (electrical) degree program. Project-based approach is chosen to strengthen these students' understanding and practical skills. Each year's project involves challenges for the students to solve by implementing...
A new technique for computing the truncated cube of an operand at length of power two is proposed, implemented, analyzed, and compared to existing techniques. The new proposed method is comparable to previously proposed methods that compute the cube of an operand in parallel. Post layout results are presented in a 65nm Application Specific Integrated Circuit implementation and are compared against...
This paper proposes a novel aspect and transaction oriented programming, design and verification language (PDVL). The electronic system level (ESL) language is inspired by SystemVerilog, SystemC and many others, but adds for example program paradigms such as aspect and transaction oriented programming. To name a few improvement over existing languages, the method to define inverse transactions is...
Due to the proliferation of reprogrammable hardware, core designs built from modules drawn from a variety of sources execute with direct access to critical system resources. Expressing guarantees that such modules satisfy, in particular the dynamic conditions under which they release information about their unbounded streams of inputs, and automatically proving that they satisfy such guarantees, is...
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