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Power consumption is a major concern in nearly all systems, from data centers to portable devices and medical implants. Consequently, effective power management is increasingly important to designers working in a wide range of application domains. This session collects eight papers addressing the most recent advances in circuits and control strategies for power management.
This paper analyses comb-based decimation structures for Sigma-Delta Analog-Digital Converters (ADCs), with high even decimation factors. The topology under study has two stages: the first stage is a non-recursive-comb and the second one is a CIC (Cascaded-Integrator-Comb) structure. As a result, efficient structures are identified in terms of the power consumption and silicon area. Additionally,...
Routing has been considered as one of the most important issues in 6LoWPAN [22] networks. For this reason, the Internet Engineering Task Force (IETF) has proposed a routing protocol called RPL (Routing Protocol for Low Power and Lossy Networks). This paper presents a performance evaluation of the repair mechanisms of RPL with storing mode, using the Contiki simulation environment. Performance metrics...
A passive 2nd-order sigma-delta modulator based on a cascade of first-order lowpass filters was designed, fabricated, and tested. A lumped RC filter is added in the loop of a conventional 1st-order passive sigma-delta modulator in order to improve the linearity of its transfer function. A low power edge-triggered comparator was designed and fabricated along with lumped components in ON Semiconductor's...
In this work a new resistorless sub-bandgap voltage reference topology is presented. It is a self-biased and small area circuit that works in the nano-ampere consumption range, and under 1 V of power supply. The behavior of the circuit is analitically described, a design methodology is proposed and simulation results are presented for a standard 0.18 µm CMOS pr°Cess. A reference voltage of 463 mV...
A low-power high-resolution Delta-Sigma modulator for audio codec, designed in Global-Foundries BCD 0.18µm 1P4M CMOS process, is presented. The modulator employs a fourth-order single-loop feedforward topology with a 3bit-quantizer. A novel structure of Switched-Opamp (SO) utilizing current-starvation and Slew-Rate (SR) boosting is adopted to meet the requirements of high performance and fast settling...
This paper presents the reviews of few previous works for low noise amplifier design (LNA). This paper will explore several recent architectures of LNA but focused on four techniques of topologies which are forward body bias, self-biased inverter, common source cascade and cascode technique. Those architectures are able to minimize power consumed in a typical CMOS for wireless sensor network (WSN)...
This paper proposes a multiple-channel frontend system with current reuse for fetal monitoring applications. The structure and specifications of the proposed frontend system are determined while taking into consideration the algorithms used for fetal electrocardiogram (fECG) detection. Two amplifier topologies based on a middle rail current source/sink (MCS) are proposed for fECG and electrohysterogram...
The comparator-based asynchronous binary-search (CABS) analog-to-digital converter (ADC) topology is a good solution to achieve high conversion rate at low power dissipation. In this paper we present an architecture of CABS ADC with a background calibration scheme, that allows the use of smaller devices, further reducing the power consumption. Unlike the foreground calibration, it does not require...
The so-called scale free property is a feature of many complex systems, including the Internet and World Wide Web, where most nodes have just a few links whereas the rest have a huge number of them. The traditional models conceived to reproduce the formation of these systems do not take into account the topological features of the growing network. Nevertheless, the resulting topology has a major influence...
Average consensus algorithms are an essential tool in wireless sensor networks for multiple estimation tasks, being the convergence time and the energy consumption of these algorithms critical for their usability. Most existing work in the related literature focuses on improving these two parameters, assuming generally unicast communications, which are neither realistic nor efficient given the wireless...
This paper presents a 10 Gbps loss of signal (LOS) detector for high-speed AC-coupled serial transceivers. The detector is designed in 28nm CMOS and is capable of operating with a 29.5mV internal eye opening and a 67mV external eye opening at the input pads. It consumes 69uW from a 0.9V supply at 10 Gbps and properly asserts an LOS state in 6.8 nsec. A novel comparator topology, which is a part of...
This paper considers the problem of logical topology selection in an IP-over-WDM network, with the objective to minimize the total power consumption used to support the traffic demands. While there are several power consuming devices in a backbone WDM network, it is assumed that major power consumption occurs at IP router ports, which are termination points of optical connections or lightpaths. The...
This paper examines the fault ride-through strategy of a three-phase PV system with respect to compliance to the German Transmission Code. Specifically, the paper examines the case of a single line-ground fault which occurs predominantly in the distribution system. The paper proposes the injection of reactive power on a perphase basis to the faulty phases while maintaining active power injection to...
The conventional binary weighted array SAR ADC is the common topology adopted to achieve high efficiency conversion, i.e. with less than 10 fJ/conversion-step, even requiring extra effort to design and simulate full custom sub-fF capacitors. This paper presents the design and the optimization of an asynchronous SAR ADC with attenuation capacitor achieving an efficiency similar to conventional binary...
Access networks are responsible for a significant part of overall telecom network energy consumption. Furthermore their demand for energy also increases rapidly with the ever-growing traffic volume they carry. Sustainability necessitates energy conserving solutions which also carefully limit the negative effects on other system qualities. It is expected that future access networks are based on a converged...
Data center power optimization has recently received a great deal of research attention. For example, server consolidation has been demonstrated as one of the most effective energy saving methodologies. Likewise, traffic consolidation has also been recently proposed to save energy for data center networks (DCNs). However, current research on data center power optimization focuses on servers and DCN...
Time slotted channel hopping (TSCH) and coordinated sampled listening (CSL) are two of the main features of IEEE 802.15.4e designed for wireless sensor networks (WSNs). In this paper, we compare the power and latency performance of TSCH and CSL for various scenarios. Our results show that while TSCH outperforms CSL in terms of power, its latency is higher.
Power-gating is a promising technique to mitigate the increasing static power of on-chip routers. Clos networks are potentially good targets for power-gating because of their path diversity and decoupling between processing elements and most of the routers. While power-gated Clos networks can perform better than power-gated direct networks such as meshes, a significant performance penalty exists when...
<?Pub Dtl?>A high-performance buffer amplifier topology for liquid crystal display drivers is presented. The proposed amplifier achieves fast driving performance and offers a rail-to-rail common-mode input range. Enhanced slewing and settling capabilities are achieved through a novel output stage performing dual-path push-pull operation. No additional biasing network is required to set the quiescent...
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