The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the...
Test mode power dissipation has been found to be much more than the functional power dissipation. Since dynamic power dissipation had a major contribution to the heat generated, most of the studies focused on reducing the transitions during testing. But at submicron technology, leakage current becomes significantly high. This demands a control on the leakage current as well. In this work, we propose...
Threshold testing, which is an LSI testing method based on the acceptability of faults, is effective in yield enhancement of LSIs and selective hardening for LSI systems. In this paper, we propose test generation models for threshold test generation. Using the proposed models, we can efficiently identify acceptable faults and generate test patterns for unacceptable faults with a general test generation...
Development in electrical power transmission system requires the use of circuit breakers with increasing breaking capacity. At present circuit breakers are to be installed on 245 kV to 1100 kV power system with short circuit ratings up to 120 kA. To test high voltage CBs, direct testing using the power system or short circuit alternators are not feasible. The testing of high voltage CBs of larger...
Stress optimization for memory devices is a complex process due to the continuous space of possible optimization values for relevant parameters. This paper uses a method based on electrical Spice simulation to perform this optimization process for DRAM devices. The paper presents a case-study performed in Qimonda to optimize the timing and temperature stresses for the strap problem in defective memory...
Methods for testing from finite state machine-based specifications often require the existence of a preset distinguishing sequence for constructing checking sequences. It has been shown that an adaptive distinguishing sequence is sufficient for these methods. This result is significant because adaptive distinguishing sequences are strictly more common and up to exponentially shorter than preset ones...
Totally self-checking (TSC) circuit is a class of circuits which are used to detect faults concurrently with normal operation. This paper introduces a new method for designing self-checking static CMOS circuit. The designed circuit based on the proposed method can detect breaks and transistor stuck-on faults. The resulting circuit produces a valid code (00 or 11) on its output in the fault-free. Otherwise,...
Testing modeled faults multiple times has been shown to increase the likelihood of a test set to detect non-modeled faults, either static or dynamic, when compared to a single detect test set. Test sets that guarantee detecting every modeled fault with at least n different tests are known as n-detect test sets. Moreover, recent investigations examine how different the various tests for a fault should...
A method based on wavelet packets and PCA is developed for testing of analog circuits. It can detect both hard and soft faults in an analog electronic circuit by analyzing its output voltage response. The wavelet packets decomposition tree of the output voltage response is computed and the energy of every decomposed signal is used to form the feature vector. These features are combined by PCA to detect...
The complex interactions appearing in service-oriented computing make coordination a key concern in service-oriented systems. In this paper, we present a fault-based method to generate test cases for component connectors from specifications. For connectors, faults are caused by possible errors during the development process, such as wrongly used channels, missing or redundant subcircuits, or circuits...
In this paper we present a new technique called captureless delay testing points (CDTP). This technique allows the detection of delay faults left uncovered by launch-on-capture transitions, with top-off random launch-on-shift patterns that do not require fast switching scan enable signals. The CDTP random patterns are internally generated, requiring virtually no additional test time or memory tester...
Scan based timing comparison tests offer a potential solution to the problem of small delay detection in aggressive nanometer technologies. However, such tests require that circuit delays be unambiguously captured in the scan chains using multiple fast clocks. To ensure this, only those signals that are known to be hazard free at capture are analysed for timing information from the scan-out data....
This paper proposes a method to compute delay values in 3-valued fault simulation for test cubes which are test patterns with Xs. Because the detectable delay size of each fault by a test cube is fixed after assigning logic values to the Xs in the test cube, the proposed method computes a range of the delay values of the test patterns covered by the test cube. By using the proposed method, we can...
This paper presents a c-testable motion estimation (CTME) design to efficiently detect the faults in process elements (PEs). The goal of the CTME design is to offer high reliability for video coding systems. The proposed CTME was carried out by Verilog HDL and synthesized with the TSMC 0.18 mum CMOS technology. Logic simulation results show that the proposed CTME guarantees 100% fault coverage with...
An experiment comparing the efficiency of different test strategies on a moderate complexity mixed-signal circuit with 1300 nodes is presented. Selected test strategies from the groups of functional, structural and parametric approaches were considered. Bridging faults are taken into account and fault simulations results are shown, where fault coverage, efficiency and quality of the tests are evaluated.
The importance of System-On-Chip (SoC) validation continues to grow with the increase of design size. How to measure the completeness and quality of validation approach? An innovative domain coverage metric is proposed in this paper. Domain methodology is based on a geometrical analysis of the domain boundary and takes advantage of the fact that point on or near the boundary is most sensitive to domain...
The paper presents a system-level diagnosis based on a general symmetric diagnostic model - the PMC model. In particular, the one-step diagnosis of t-diagnosable systems and its Boolean formalization extension are presented. This extension transforms a syndrome decoding process to solving Boolean expressions. New rules for the PMC model were defined with their application to regular systems. Using...
This paper discusses a test generation method to derive high quality transition tests for combinational circuits. It is known that, for a transition fault, a test set which propagates the errors (late transitions) to all the primary outputs reachable from the fault site can enhance the detectability of unmodeled defects. In this paper, to generate a minimum test set that meets the above property,...
Evolutionary Computation techniques are gradually making their way into mainstream validation of complex micro-processors. In this paper, we define the validation problem within the microprocessor as well as System-on-Chip context. We also outline the evolving role of the evolutionary algorithm within the development cycle of such complex design projects. Over time, evolutionary algorithms have been...
The Distribution System Analysis Subcommittee (DSAS) of the IEEE PES Power System Analysis, Computing, and Economics Committee has been developing benchmarks for distribution system analysis tools. A number of test cases have already been developed may be easily downloaded on the Internet. Other test cases have been requested. This paper describes the purpose and planned direction for these test cases...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.