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The aviation industry has many aircraft in use after more than twenty years of life with some aircraft achieving the fifty years of life milestone. The avionics aboard the older aircraft are based on circuitry elements with diminishing or no manufacturing sources. Entire families of integrated circuits are no longer available, such as the early Intel processors and peripherals, 54C series CMOS logic...
Open source hardware projects are becoming more and more common. OpenRISC SOC, one of the prominent of these projects, has become quite popular with the support of volunteer developers. In this work, we have demonstrated the design of an DES (Data Encryption Standard) based system, that can be used in security applications, on ORPSoC-v2 (Openrisc Reference Platform System-on-Chip). Additionally, we...
We present the UltraSound ToolBox (USTB), a processing framework for ultrasound signals. USTB aims to facilitate the comparison of imaging techniques and the dissemination of research results. It fills the void of tools for algorithm sharing and verification, and enables a solid assessment of the correctness and relevance of new approaches. It also aims to boost research productivity by cutting down...
Networks-on-Chip (NoCs) in chip multiprocessors are prone to within-die process variation as they span the whole chip. To tolerate variation, their voltages (Vdd) carry over-provisioned guardbands. As a result, prior work has proposed to save energy by operating at reduced Vdd while occasionally suffering and fixing errors. Unfortunately, these proposals use heuristic controller designs that provide...
Null pointer exceptions are common bugs in Java projects. Previous research has shown that dereferencing the results of method calls is the main source of these bugs, as developers do not anticipate that some methods return null. To make matters worse, we find that whether a method returns null or not (nullness), is rarely documented. We argue that method nullness is a vital piece of information that...
3D memory is becoming an increasingly popular technology to overcome the performance gap between memory and processors. It has led to the development of new architectures with scratchpad memory, which offer high bandwidth and user-controlled access features. The ideal performance of this scratchpad memory is peak bandwidth for any random block access. However, 3D memories come with their constraints...
Processors in sensor nodes offer very deep sleep modes to save energy and to increase the battery lifetime with the disadvantage that the content of the volatile memory will be typically lost in these modes. The backup and restore of data from volatile to non-volatile memories is expensive regarding the energy budget. Emerging new memory technologies offer the opportunity for new memory layouts in...
This paper presents an integrated design environment (IDE) for embedded fault-tolerant processor system. It takes in a processor core IP and the embedded software which is to be executed on the given processor, and turns them into a fault-tolerant system with various hardware and software mechanisms, subject to the designer's selection. The hardware options include dual redundancy for processor core,...
To handle the memory wall problem and satisfy the high processing speed of the multicore processors, there is significant demand for a large cache capacity in future. The 3D die-stacking DRAM cache with high density can be used as a large cache compared with conventional SRAM cache. However, energy becomes an inevitable challenge with the increasing size of DRAM cache. STT-RAM with near-zero leakage...
The widespread use of graphs to model large scale real-world data brings with it the need for fast graph analytics. In this paper, we explore the problem of triangle counting, a fundamental graph-analytic operation, on shared-memory platforms. Existing triangle counting implementations do not effectively utilize the key characteristics of large sparse graphs for tuning their algorithms for performance...
Employing an on-chip network in a manycore system (to improve scalability) makes the latencies of data accesses issued by a core non-uniform, which significant impact application performance. This paper presents a compiler strategy which involves exposing architecture information to the compiler to enable optimized computation-to-core mapping. Our scheme takes into account the relative positions of...
Multiprocessing can be considered the most characteristic common property of complex digital systems. Due to the more and more complex tasks to be solved for fulfilling often conflicting requirements (cost, speed, energy and communication efficiency, pipelining, parallelism, the number of component processors, etc.), the so called heterogeneous multiprocessor architectures (HMPA) have become unavoidable...
The advances in silicon technology lead to systems with hundreds of processors, the NoC-based MPSoCs. However, the higher fault probability in deep sub-micron technologies shortens the integrated circuits lifetime. Operating systems enable to execute distributed applications in the MPSoC processing elements (PEs). Large systems require PEs dedicated to management purposes, for example, execute the...
Heterogeneous computing platforms including both processors and field programmable gate arrays (FPGAs) represent an attractive solution for balancing software flexibility with high performance and energy efficiency of custom hardware modules. Furthermore, the dynamic partial reconfiguration (DPR) capabilities of modern FPGAs allow virtualizing the available area to support several hardware modules...
In recent times, graphic, audio and video definition has improved due to significant advancement in complex algorithms and video processing techniques. These techniques require heterogeneous and multi-core processors because of their complex computation abilities. Dual-port memories have become an essential component of CPUs because multi-core processors require significant data transfer. However,...
Various signal and image processing applications require vast acceleration in order to enable real-time processing and meet constraints in power consumption. On FPGAs these applications can be implemented as application-specific circuit. Although IP cores for various applications exist, even interfacing these usually requires experienced knowledge in hardware design. Using FPGAs or other accelerators...
This paper investigates the problem of deriving a white box performance model of Hardware Transactional Memory (HTM) systems. The proposed model targets TSX, a popular implementation of HTM integrated in Intel processors starting with the Haswell family in 2013.An inherent difficulty with building white-box models of commercially available HTM systems is that their internals are either vaguely documented...
Heterogeneous multicores provide alternative core types and potentially multiple voltage-frequency levels to execute workloads more efficiently. One fundamental obstacle for capitalizing their potential performance and energy gains is identifying the most appropriate configuration (core type and voltage-frequency pair) for executing the computations at hand. In this paper, we analyze an ARM big.LITTLE...
Achieving a power envelope of few milliwatts combined with tight performance constraints is emerging as one of the key challenges for battery-powered and low cost Internet-of-things (IoT) end-nodes. IoT devices have to cope with highly time-varying workloads, characterized by intermittent “race-to-sleep” bursts of compute-intensive operations mingled with long periods of low activity. Architectural...
Aiming at the situation of priority scheduling algorithm of chaos, later redundant processing in the task scheduling on current multi-core heterogeneous processors, this paper proposes a task scheduling algorithm with weighted priority algorithm-- WPTS. It is related to three attribute values of the main reference tasks, which can be obtained by weighted comparison that can overcome the confusion...
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