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μBIC system is a bus type independent communication system ported on ARM7 platform. μBIC is part of the MERSES project that deals with model oriented design and implementation of signal processing embedded systems. Parameters for configuration of communication interface are stored in XML format string, and in application, this system presents a simple method to build different bus systems application.
This paper presents a scalable and flexible multi-core SoC architecture for high-speed key exchange for emerging IP security systems. Novel approaches are proposed for HMAC authentication block parallelization, distributed key handling and a pipelined block cipher design that allows feedback encryption modes. This improves upon previous state-of-the-art designs for IPSec, creating an architecture...
Many new designs for Decimal Floating Point (DFP) hardware units have been proposed in the last few years. To date, only the IBM POWER6 and POWER7 processors include internal units for decimal floating point processing. We have designed and tested several DFP units including an adder, multiplier, divider, square root, and fused-multiply-add compliant with the IEEE 754-2008 standard. This paper presents...
Simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). SystemC TLM2.0 (Transaction Level Modeling) is now commonly used to accelerate the simulation. However, the standard SystemC simulation engine uses a centralized scheduler that is clearly a bottleneck to parallelize the simulation of architectures containing hundreds of processor cores, and involving...
This article proposes an original methodology for the fast prototyping of image processing on a generic MP-SoC (Multi-Processors System on Chip) architecture. To define a processors network adapted to a particular application is critical and design-time consuming in order to achieve high-performance customized solutions. The effectiveness of such approaches largely depends on the availability of an...
Energy efficiency is a primary concern for microprocessor designers. A very effective approach to improving the energy efficiency of a chip is to lower its supply voltage to very close to the transitor's threshold voltage, into what is called the near-thresold region. This reduces power consumption dramatically but also decreases reliability by orders of magnitude, especially for SRAM structures such...
This paper proposes Flex Core, a hybrid processor architecture where an on-chip reconfigurable fabric (FPGA) is tightly coupled with the main processing core. Flex Core provides an efficient platform that can support a broad range of run-time monitoring and bookkeeping techniques. Unlike using custom hardware, which is more efficient but often extremely difficult and expensive to incorporate into...
Modern processor architectures sacrifice timing predictability to improve average performance. Branch prediction, out-of-order execution, and multi-level cache hierarchies complicate accurate execution time estimates. The timing demands of Cyber Physical Systems (CPS) have led some to propose new processor architectures, including Precision Timed (PRET) processors, which simplify analysis of execution...
The increasing failure rates observed in very deep sub micron silicon technologies pose a major problem to the design of future high-density SoCs. Emerging new architecture based on Multiprocessor SoC (MPSoC) gives the opportunity to exploit the natural redundancy with replicated spare processor in order to maintain the system performance in presence of failures. Based on the assumption that a transient...
We propose a minimalistic processor architecture tailoring Wave Field Synthesis (WFS)-based audio applications to configurable hardware. Eleven high-level instructions provide the required flexibility for embedded WFS customization. We describe the implementation of the proposed instructions and apply them to a multi-core reconfigurable WFS architecture. Our approach combines software programming...
In this paper we study the feasibility of instruction set specialization for reconfigurable ASIPs at runtime. Applying known instruction set extension algorithms for static ASIPs in this just-in-time CPU specialization context is generally possible. However, the leading state-of-the-art algorithms for this purpose have an exponential algorithmic complexity which is prohibitive when targeting large...
X86 emulation on heterogeneous processor platform suffers from low performance and other problems, to solve these problems, a kind of high performance IO architecture was presented. This paper describes the design and implementations in details. At last, SPEC2000 benchmark test result showed that this IO architecture's performance is higher than the software simulation technology.
The Instruction Set Architecure (ISA) of micro-processors is usually word oriented, so it is not optimized to perform bit level operations. A functional unit oriented to the bit manipulation could accelerate the computation increasing the microprocessor performance in terms of execution time. This work presents the experimental results of the integration between the Bit Manipulation Unit (BMU) described...
Exploiting the locality of blocks in the same set, LRU replacement strategy has deficiencies to manage L2 cache resources as the temporal locality has filtered by L1 caches. Instead, reuse replacement strategy develops the reuse characteristics of blocks in entire cache scope being more potential to improve cache resources utilization. We use reuse replacement to manage L2 cache resources in chip...
This paper presents our integrated system-level design tool set, named Advanced SystemBuilder. Advanced SystemBuilder supports overall methodology for system design and design space exploration, and provides programming model of systems, automatic synthesis capabilities for FPGA-based prototyping, cosimulation and execution profiling. A case study of MPEG4 decoder design shows the effectiveness of...
This article proposes an original design flow for the fast prototyping of image processing on a MP-SoC (MultiProcessors System on Chip) architecture. Developing processors network systems tailored to a particular application domain is critical and design-time consuming in order to achieve high-performance customized solutions. The effectiveness of such approaches largely depends on the availability...
As the number of transistors in microprocessors increases, their power demand increases accordingly. This poses design challenges for their power supply module called VRM (Voltage Regulator Module) especially when operated at sub voltage range. This paper presents the design of a new multiphase multi-interleaving topology that addresses these challenges. A lab scaled hardware prototype of the new...
As an important implementation of Cryptographic algorithm, processor should be thought about the ability of resistant power attack. In this paper we show a processor architecture, which automatically detects the execution of the encryption algorithms, and interleaves the execution of cryptographic algorithm code with that of dummy instructions to reduce the correlations between the leakage and the...
A data frame synchronization sequence processor in HiNoC receiver is implemented in this paper. It is the important module for channel estimation and channel correction. 63-point FFT, phase extracting method and so on are presented considering hardware resource. The design has been fabricated with SMIC 0.13um technology.
Multimedia embedded systems require high performance specific computation to process the large among of data that characterizes the multimedia domain at low energy consumption due to battery life. Different optimizations at different levels can considerably improve performance and energy consumption and, after that, the address generation becomes the new performance bottleneck. This paper shows a...
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