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In this paper, we present a performance comparison of Binary Coded Decimal (BCD) Adders on Field Programmable Gate Logic (FPGA) for functional and behavioural verification. Although it does not prove that the circuit is reversible, implementation on FPGA serves as a platform for functional verification of circuits. BCD adders are one such circuit which has gain wide research emphasis where BCD adders...
Spatial image filters are one of the primary operators in digital image processing and edge detection is one of their most well-known operations. Because of growing demand in applications such as real time video processing and stream image processing, accelerating this family of algorithms based on FPGA platforms has received increased attention. This paper introduces a new implementation of this...
This paper is on FPGA based emulation which is one the approaches to perform pre-silicon SoC validation, accelerate system software development and to meet time-to-market demands. This paper presents a verification methodology of SoC and also deals with simplified implementation of complex clock designs in FPGA are presented, which needs to be skillfully handled to meet the said criteria. Each base...
Of the various onboard data compression techniques used in image processing, DPCM is one of the most commonly used. This paper presents a variant of DPCM based image compression technique called DPCM-ML. DPCM-ML is an effective technique for compressing images with high degree of contrast. This paper explains the DPCM-ML technique and the implementation methodology used. For the hardware implementation,...
The Advanced Encryption Standard (AES) is specified as the cipher algorithm in IEEE 802.15.4 protocol and other industrial wireless networks protocols based on IEEE 802.15.4. But the huge computation overhead of the traditional AES implementations makes AES hard to be performed on the resource-constrained industrial wireless nodes. Although the software implementations based on 4 lookup tables and...
High-speed hardware for Keccak, which was selected as a new standard hash function named SHA-3, was developed and its performance was evaluated against SHA-1 and −2 circuits through the use of various FPGA platforms. The results showed that Keccak is suitable for high-speed hardware implementations, but it is getting harder to implement on new FPGA devices, due to the current trends in architecture...
This paper present new approaches for in-system, trace-based debug of High-Level Synthesis-generated hardware. These approaches include the use of Event Observability Ports (EOP) that provide observability of source-level events in the final hardware. We also propose the use of small, independent trace buffers called Event Observability Buffers (EOB) for tracing events through EOPs. EOBs include a...
Field Programmable Gate Arrays (FPGAs) are an ideal platform for building systems with custom hardware accelerators, however managing these systems is still a major challenge. The OpenCL standard has become accepted as a good programming model for managing heterogeneous platforms due to its rich constructs. Although commercial OpenCL frameworks are now emerging, there is a need for an open-source...
Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization...
Soft processors have been commonly used in FPGAbased designs to perform various useful functions. Some of these functions are not performance-critical and required to be implemented using very few FPGA resources. For such cases, it is desired to reduce circuit area of the soft processor as much as possible. This paper proposes Ultrasmall, a small soft processor for FPGAs. Ultrasmall supports a subset...
This paper presents a new technique to be used in the context of reconfigurable computing to accelerate the online diagnosis of permanent damage on Xilinx FPGAs using Built-In Self Tests (BISTs). Detecting and locating permanently damaged resources with precision is central to keep the system implemented on the FPGA flawless at all times; i.e. upcoming hardware tasks are mapped to available functional...
This paper presents a technique for achieving reduced input current ripple in multi-phase power converters that provide multiple heterogeneous power rails, such as that present in portable electronics or computers. Through asymmetric interleaving of individual phases, the input current ripple of the power converter can be reduced compared to conventional, symmetric interleaving. We analyze the practical...
We have developed the first FPGA-based digital physical unclonable function (PUF) by leveraging the reconfigurability of an FPGA and introducing a new way of using the standard analog delay PUF. The key observation is that for any analog delay PUF, there is a subset of challenge inputs for which the PUF output is stable regardless of operation and environmental conditions. We use only such stable...
FPGAs are commonly used in high performance computing applications, often in the form of streaming systems which exploit parallelism of algorithms along pipelined kernels. While such applications have traditionally been designed at the Register Transfer Level (RTL), the increasing complexity in terms of FPGA resource usage, arithmetic logic and dataflow is causing the time taken for RTL programming...
Hardware Trojan horses are a realistic threat for both ASIC and FPGA systems. Ring Oscillators (ROs) can be used to detect the presence of malicious hardware functionality. The length of an RO is a significant parameter for detecting efficiently malicious logic (sensitivity) while maintaining a low space and power profile. We explore through simulation the effect of the RO length on detecting different...
Function evaluation is an important arithmetic computation in many signal processing applications, such as the special function unit in modern graphics processing units (GPUs). Lookup table (LUT) usually takes a significant portion of total area in function evaluation using piecewise polynomial approximation. Many papers have proposed various approaches to reduce table size without sacrificing precision...
Cryptographic hash functions have many security based applications, particularly in message authentication codes (MACs), digital signatures and data integrity. Secure Hash Algorithm-3 (SHA-3) is a new cryptographic hash algorithm that was selected on 2nd Oct '12 after a five year public contest organized by the National Institute of Standards and Technology (NIST), USA. This paper provides a unique...
Point Multiplication (PM) is considered the most computationally complex and resource hungry Elliptic Curve Cryptography (ECC) related mathematic operation. The design of PM hardware accelerators follows approaches that have a trade off between utilized hardware resources and computation speed. In this paper, the above trade-off and its relation with the operations of the GF(2k) defining the Elliptic...
With the advancement of Electronics and IC technology, the use of controllers and processors increased drastically in the last two decades to solve complex problems efficiently with better accuracy and fast time being response. When the complexity of the problem is very high and proper mathematical model of the problem is unknown, general purpose processors or controller do not serve useful purpose...
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