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Recently, the rapid development of VoIP has attracted considerable attention. However, VoIP service exposes weakness on voice quality such as delay and jitter. So it is helpful to improve the quality of VoIP service by mitigating time latency and jitter. In this paper, VoIP phone is implemented by open source software components using the Session Initiation Protocol (SIP) based on embedded systems...
A hybrid simulator is a simulator which embeds a hardware experiment in a numerical simulation. However, the hybrid simulator is generally subjected to an inherent problem of energy increase in collision of two hardwares in the loop because of delay times. To solve this problem, Osaki et al. proposed a compensation method of delay time that can realize a variable coefficient of restitution [1]. However,...
Ethernet passive optical network (EPON) is becoming more popular since the users demand more bandwidth each day. A lot of simulation studies have been done in order to study the upstream EPON transmission, but they are less accurate due to assumed parameters and it does not take into account the physical parameters and the non-linear effects of the optical components. Therefore, this paper presents...
In this work, we are about to introduce a high performance NetFPGA based network measurement system, called Rnetprobe that implements a dual, multi-layer timestamping method for QoS analysis. The multi-layer timestamping idea came from the demand to perform end-to-end active measurements that enable improved cross-layer analysis to evaluate QoS for time sensitive services. Accordingly, for each captured...
This paper proposes a composite instruction for path setup and partitioning of a network on chip using segmented buses. The network connects a distributed memory to a coarse grained reconfigurable architecture. The scheme decreases the partitioning and routing instruction in sequencers (S) for the nodes (N) from Nx3 to a single instruction. This reduction in instruction also bear a small performance...
This work presents a synthesis framework that generates a formally verifiable RTL from a high level language. We develop an estimation model for area, delay and power metrics of arithmetic components for Xilinx Spartan 3 FPGA family. Our estimation model works 300 times faster than Xilinx's toolchain with an average error of 6.57\% for delay and 3.76\% for area estimations. Our framework extracts...
Cloud Computing (CC) is a technological phenomenon that is becoming more and more important. Also Small and Medium Enterprises (SMEs) can increase their competitiveness by taking advantage of CC. This new computing approach promises to provide many advantages, and many SMEs are encouraged to use it. However, CC is still in its early stage -- for this reason we think that it is very important to study...
Push-to-Talk over Cellular (PoC) system is ideal for group communication in many cooperative work environments because of its wider coverage and more flexibility than traditional trunk communication systems. The long session-setup-delay is an important problem that must be solved before the commercial application of PoC system. Many research works have been done to solve it in some mobile networks,...
In the previous papers, we presented a new mesh of trees based switch architecture, denoted as MOTS (N) switch, along with its variations IMOTS (N) and IMOTS-CT (N) switches. The analysis and simulation results were presented that all of them achieve 100% throughput and the mean cell delay of IMOTS-CT (N) is comparable to that of OQ switch with FIFO queues (FIFO-OQ). Especially, IMOTS-CT (N) was proposed...
The hardware implementations of decimal arithmetic operations, which are commonly used in financial, scientific, and internet-based applications requiring accuracy and speed, become prominent. In this paper we first analyze the column sum boundaries of n-digit parallel decimal array multipliers (PDAM). A general form of the problem is formed and a heuristic solution is found with Genetic Algorithm...
The 3N encoding process can simply add the input data N to its 1-bit left-shifted value 2N using the combinational digital circuits, such as ripple carry adder (RCA) or carry look-ahead adder (CLA). This paper presents an efficient algorithm and its hardware implementation. Results show that the proposed RCA-like 16-bit encoder achieves 25% less in hardware cost and 50% faster in speed performance...
This paper presents a new approach of using the improved hybrid LUT-based architecture for the low-error and efficient fixed-width squarer circuits. By employing both LUT-based and simple conventional logic circuits, the good trade-off between hardware complexity and performance can be achieved. Moreover, the mathematical identity of squaring operation is exploited so that the error can be reduced...
This paper describes a design for a variable fractional delay (VFD) FIR filter implemented on reconfigurable hardware. Fractionally delayed signals are required for several audio-based applications, including echo cancellation and musical signal analysis. Traditionally, VFD FIR filters are implemented using a complex, fixed structure based upon the order of the filter. This fixed structure restricts...
The growing market for Digital Signal Processing (DSP), Computer graphics and embedded systems applications that can be modeled as polynomial computations in their datapath designs, requires improvements in high-level synthesis and optimization techniques for such systems. This paper concentrates on how to find common sub-expressions between s given polynomial functions over Z2n1 × Z2n2 × … × Z2nd...
This paper presents two fully synthesizable and emulation friendly delay cell designs that the authors have successfully implemented in a real emulation environment. Due to the analog nature of delay logics, none of the commercial emulators were able to support the actual delay behavior. Thus, manual additions of register were needed for each customized scenario. The effort required is huge and highly...
Exploiting computational precision can improve performance significantly without losing accuracy in many applications. To enable this, we propose an innovative arithmetic logic unit (ALU) architecture that supports true dynamic precision operations on the fly. The proposed architecture targets both fixed-point and floating-point ALUs, but in this paper we focus mainly on the precision-controlling...
Traditional network processors (NPs) adopt pull model, where NP cores pull packet data from external memory to local memory, triggered by cache miss or fetch instructions. Due to the long latency of data fetching, hardware multithreading is typically used to reduce the waiting time. Multithreading incurs context switch overhead, leading to inefficiency in payload processing applications. We propose...
Over the past two decades, several microarchitectural side channels have been exploited to create sophisticated security attacks. Solutions to this problem have mainly focused on fixing the source of leaks either by limiting the flow of information through the side channel by modifying hardware, or by refactoring vulnerable software to protect sensitive data from leaking. These solutions are reactive...
Because of the ever increasing number of cores present on a single chip, fast and energy efficient, inter-core data communication has become a major concern. Various networkon-chip (NoC) topologies and flow controls have been presented in literature. In this paper, for the first time, the benefits of a hierarchical heterogeneous NoC are quantized using a comprehensive circuit-interconnect technology...
Mitigation of radiation effects is one of the major problems for space-borne computing platforms. The presented work proposes an approach for building reliable, hardware fault adaptive stream processing platforms for space applications. The proposed concept is based on architecture-to-fault adaptation by run-time hardware reconfiguration. The concept assumes representation of system components in...
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