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Testing digital circuits is crucial for guaranteeing the correct and reliable functioning of electronic devices. Deriving high quality test suites to check the correctness of such devices is an important task. To estimate the quality of a test suite, a common approach is to simulate faults in a given circuit specification and to assess the fault coverage of the test suite. In this paper, we propose...
This paper presents a unique and efficient artificial neural network (ANN) based fault detection, classification and location on part of the Nigerian 132kV transmission line. The objective is to evaluate the performance of ANN based relays connected at both ends of the lines using feed-forward non-linear supervised back propagation algorithm with Levenberg-marguardt network topology. Using the PSCAD/EMTP...
In order to have proper operation of the “relay” protection devices, their behavior shall be studied and tested for different possible operational conditions. The harmonic spectrum in the supervised circuits may affect the protection functions. Harmonics can be generated in the primary circuits by faults, non-linear loads, converters, etc. Harmonics can also be induced in the secondary circuits by...
This paper presents a mathematical model for assessing the availability of a non-redundant telecommunications system, which is continuously tested during operation. The types of faults that can occur in such systems are defined as permanent and intermittent faults. Mathematical equations are derived to calculate the mean times spent by the system in the operable and repair states using the properties...
An automatic, defect-oriented method is proposed for activating latent defects in analog and mixed-signal integrated circuits. Based on the topology modification technique, added stress transistors generate voltage stress that activates these latent defects. This contrasts with burn-in testing which uses increased temperatures as a fault activation mechanism. Moreover, this Design-for-Testability...
Physical defects in capacitive MEMS devices can change the nominal device capacitance by a few femtofarads. Detecting such small variations is challenging particularly in the presence of Process, Temperature, and supply Voltage (PVT) variations. A test solution utilizing a phase locking circuit is presented in this paper to minimize the effect of PVT variations on fault detection. A Delay Locked Loop...
Digital microfluidic biochip (DMFB) is an attractive platform for immunoassays, point-of-care clinical diagnostics, DNA sequencing, and other laboratory procedures in laboratory experiments due to its flexible application and low fabrication cost and further for the development of instruments. As being applied for these safe-critical applications, on-line testing methods are required to ensure robust...
The quality level of the analog parts in mixed-signal ICs lags behind the below-part-per-million escape rates of the digital core. The reason is that analog blocks in these ICs have high test escape rates as a result of the typical testing based on performance specifications. Test point selection/insertion techniques have been proposed to solve this problem by offering increased observability. However,...
Scan attacks exploit facilities offered by scan chains to retrieve embedded secret data, in particular secret keys used in crypto-processors for encoding information in such a way that only knowledge of the secret key allows to access it. This paper presents a scan attack countermeasure based on the encryption of the scan chain content. The goal is to counteract the security threats and, at the same...
Power distribution equipment is the backbone of any industrial process infrastructure. Safety and reliability are the two most important criteria in the proper functioning of the power distribution system. Low-voltage switchgear (LVS) is an important part of power distribution. Minimizing arc faults in the switchgear is a matter of utmost concern to maintain a safe environment. Arc-resistant LVS is...
Pole mounted transformers are subject to inrush currents, that occur during start-up of the transformer. The inrush currents may cause unwanted forces on the windings. Testing was done at a Transformer Testing Facility to develop a model to understand the inrush currents. The model matched measured results closely.
Adaptive test is a promising direction for reducing the manufacturing test cost. It aims to dynamically adjust the test program on a device-by-device or on a wafer-by-wafer basis. Adjusting the test program could involve eliminating tests, changing test limits, re-ordering tests, etc. The objective is to spend the minimum possible test time per device without sacrificing fault coverage. In this paper,...
In recent years early life failures have caused several product recalls in semiconductor and automotive industries associated with a loss of billions of dollars. They can be traced back to various root-causes. In embedded or cyber-physical systems, the interaction with the environment and the behavior of the hardware/software interface are hard to predict, which may lead to unforeseen failures. In...
In the recent technological advancements, Automotive industry is more concentrating towards passenger safety. As a result modern Automobiles may have more than 50 electronic control unit on them. The verification of these ECUs is a necessary and crucial task. The manual testing involves human interaction for stipulating input and observing outcomes, hence it is not only time consuming but may involve...
Despite analog SPICE-like simulators have reached their maturity, most of them were not originally conceived for simulating faulty circuits. With the advent of smart systems, fault testing has to deal with models encompassing both analog and digital blocks. Due to their complexity, the industry is still lacking of effective testing approaches for these analog and mixed-signal (AMS) models. The current...
Fully Programmable Valve Array (FPVA) has emerged as a new architecture for the next-generation flow-based microfluidic biochips. This 2D-array consists of regularly-arranged valves, which can be dynamically configured by users to realize microfluidic devices of different shapes and sizes as well as interconnections. Additionally, the regularity of the underlying structure renders FPVAs easier to...
In the last years, the phenomenon of electronic products passing all tests by the manufacturer but failing in the field (No Fault Found, or NFF) attracted the attention of industries and researchers. Delay faults are supposed to be among the contributors to this phenomenon. Hence, companies are increasingly adopting functional test as a final step, which is expected to detect this kind of defects...
Fault masking happens when the effect of one fault serves to mask that of another fault for particular test inputs. The coupling effect is relied upon by testing practitioners to ensure that fault masking is rare. It states that complex faults are coupled to simple faults in such a way that a test data set that detects all simple faults in a program will detect a high percentage of the complex faults...
As technology scales, small and dense geometries, and process variations introduce defects that are often not detected by single stuck-at tests. To improve defect coverage, we expand the single stuck-at tests to cover multiple stuck-at faults. This paper investigates multiple stuck-at fault (MSAF) testability of ROBDD (Reduced Ordered Binary Decision Diagram) based fully delay testable combinational...
Logic Selectivity immensely reduces both number of outages and their duration in the distribution network. IEC 61850 can be applied for standard implementing of Logic Selectivity in which Generic Object Oriented Substation Events (GOOSE) messages should be exchanged between intelligent field devices over the Internet. However, information security and automation requirements must be noted in order...
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