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Mitigation of radiation effects is one of the major problems for space-borne computing platforms. The presented work proposes an approach for building reliable, hardware fault adaptive stream processing platforms for space applications. The proposed concept is based on architecture-to-fault adaptation by run-time hardware reconfiguration. The concept assumes representation of system components in...
State of the art radiation tolerant SRAM-based FPGAs with large gate count offer powerful processing capability among devices qualified for space applications. Due to changing mission requirements the processing in a space instrument needs to be adaptable. Modern SRAM-based FPGAs can be partially and dynamically reconfigured and thereby offer a method of adaptability. To provide a flexible communication...
This paper deals with the management of a SoC-based current controller using an efficient Real-Time Operating System (RTOS). To accelerate the services of this operating system, a Real-Time Unit (RTU) was developed in VHDL and associated to the RTOS. It consists in hardware operating system that moves the scheduling and communication process from software RTOS to hardware. Thus, a significant acceleration...
The use of the Karhunen-Loéve Transform (KLT) for spectral decorrelation in compression of hyperspectral satellite images results in improved performance. However, the KLT algorithm consists of sequential processes, which are computationally intensive, such as the Covariance and Eigenvector evaluations, etc. These processes slow down the overall computation of the KLT transform significantly. The...
This paper focuses on the assertion-based verification (ABV) of hardware/software embedded systems, described at the Electronic System Level. We first summarize the features of a tool that enables the automatic instrumentation of SystemC TLM platforms with property checkers produced from PSL assertions and the runtime verification of these requirements. We also present its last improvements. Then...
This paper proposes a service-oriented reconfigurable co-processing architecture. The novelty of the architecture is to apply service-oriented concepts to system on chip (SoC) design paradigms and utilizes each processor and IP core as a function unit. Regarded as abstract instructions, tasks can be scheduled to IP core for parallel execution automatically. A uniform IP reconfiguration interface is...
In this paper we present the power optimization of a GNSS, Bluetooth, FM radio combo SoC for smartphones and tablet devices. The optimization ranges from architectural level, clock management level and RTL level. The techniques of power state and power control, clock gating, clock distribution, operand isolation and logic grouping have been tailored to the specific needs of wireless combo SoC. The...
The paper presents a system-on-chip (SOC) aimed to provide the fast video stream processing and wireless transfer for automotive applications, e.g. from a truck's trailer to the driver cabin. This SOC is based on the ARC processor and a custom very-low-latency video codec. It is verified and implemented in FPGA on a custom printed-circuit-board. The very first test results are presented too.
One of the concepts of smart grid is to have direct communication from power utilities to communities with immediate response for critical electricity situation. Smart Energy Home Area Network (SE HAN) devices having the ability to response for demands from power utilities are important parts of the smart grid network. ZigBee Smart Energy Profile (SEP) is widely used for trial and pilot programs but...
When migrating to future technology nodes, dependability becomes a major design problem as variability, aging and susceptibility to soft errors increase. The purpose of this program is to research cross-layer solutions that address the physical problems at system-level i.e. at hardware-level, operating system level, application level etc. The goals and an overview of the DFG SPP 1500 research program...
Control systems are widely used in several industrial applications fields. The most traditional control system, the Proportional, Integrative and Derivative (PID) controller, has long been implemented through several different technologies. In the last two decades, the widespread use of Field Programmable Gate Arrays (FPGAs) led to the development of several dedicated digital hardware PID modules...
In recent years the wide spread introduction of small embedded systems into every corner of everyday life lead to the strong need for highly reliable and secure computing machines. These machines now affect the safety of humans as well as the security of personal data and consequently money transactions. To ensure the integrity of these systems' operating state, several fault detection mechanisms...
In this paper, we address the hardware overhead of the dynamically reconfigurable functional unit (DRFU) in dynamically reconfigurable processors (DRP), in the context of low-power, embedded system-on-chips (E-SoC). We consider a tightly coupled DRP with a small, coarse-grain DRFU made of four columns of four ALUs. These are interconnected following one of the following interconnection scheme: direct...
In the hardware design of ME, memory bandwidth and on-chip memory size are major constraints to be considered, especially for mobile video encoder, so as to reduce power consumption and area. In a spatial scalable video encoder, with limited memory bandwidth and on-chip memory size to fetch and store reference frames, the search window for enhancement layer (EL) becomes relatively smaller than that...
This paper presents a software-hardware co-operative protocol processor for a 10 gigabit Ethernet passive optical network (10G-EPON), designed with a software-hardware division technique that focuses on the throughput and timing-accuracy requirements. This protocol processor consists of frame-processing hardware to meet the timing requirements, an interface to absorb the speed difference between software...
Network-on-chip based multicore systems need efficient management of a multitude of processing resources, hence avoiding hardware and system software from making inefficient time- and power-decisions at runtime. Hardware event management is a necessary path to assist in high-speed management of captured events and enable efficient reaction mechanisms. This paper proposes different micro architecture...
Based on 32-bit reduced instruction set computing (RISC) CPU architecture, Andes's CPU series are called AndesCore which support designers to exploit SoC platform. Three major application classifications that N8, N9, N10 and N12 can be deployed to, are entry level MCU based application, mid range Linux or RTOS application, and high end Linux application, respectively. Each of N8, N9, N10 or N12, namely...
Analytical modeling is becoming an increasingly important technique used in the design of chip multiprocessors. Most such models assume multi-programmed workload mixes and either ignore or oversimplify the behavior of multi-threaded applications. In particular, data sharing observed in multi-threaded applications, and its impact on chip design decisions, has not been well characterized in prior analytical...
As network link rates are being pushed beyond 40 Gbps, IP lookup in high-speed routers is moving to hardware. The TCAM (Ternary Content Addressable Memory)-based IP lookup engine and the SRAM (Static Random Access Memory)-based IP lookup pipeline are the two most common ways to achieve high throughput. However, route updates in both engines degrade lookup performance and may lead to packet drops....
In wireless networks, base stations are responsible for operating on large amounts of traffic at high speed rates. With the advent of new standards, as 4G, further pressure is put in the hardware requirements to satisfy speeds of up to 1 Gbps. In this work, we study the applicability and potential benefits of the IBM PowerEN processor (a multi-core, massively multithreaded platform) in the realm of...
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