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In this work, we present an integrated 230–310 GHz heterodyne down converter in 65 nm CMOS technology. The circuit includes a mixer and a local oscillator based on a Colpitts topology VCO. The on-chip oscillator generates a 88–95 GHz fundamental tone but drives the mixer with the 3rd harmonic around 270 GHz. The down converter measured conversion loss is about +25.5 dB around 280 GHz. The measured...
This paper presents the design and characteristics of a receiver and a transmitter in 65-nm CMOS technology for automotive radar systems covering dual radar bands of 76 GHz and 79 GHz. The receiver has a 4-channel fully differential configuration for DBF systems. A unit receiver achieves a single-side band noise figure of 12 dB at an IF range from 1 to 200 kHz using a low 1/f-noise double-balanced...
This paper presents a low-power CMOS single-chip transceiver for sub-GHz wireless sensor network applications, which complies IEEE 802.15.4-2012 standard. It embodies RF transceiver section based on direct-conversion transmitter and low-IF receiver architecture. To validate its operation, the prototype is fabricated in 0.18um GF standard CMOS process. It shows +5dBm TX output power and −85dBm RX sensitivity...
This paper suggests 60 GHz non-coherent OOK receiver which is a strong candidate for 5G near filed communications in Korea. The receiver consists of a fully differential envelop detector and a limiting amplifier. The measured receiver shows 32 dB peak gain at −28 dBm input power level. The sensitivity of the receiver is measured −25 dBm under 3 Gbps data rate. The proposed receiver is fabricated with...
Since the first OC-192 transceiver in CMOS was introduced in 2000, architecture and technology advancements have pushed wireline transceivers in CMOS to mainstream, even for OC-768 data rates. A diverse portfolio of multi-gigabit SerDes I/Os is now essential for large scale SOCs, not only for Networking but also Consumer applications. DSP-based transceivers with ADC frontends have forced a paradigm...
High-bandwidth wireline communication continues to be crucial for many electronic systems today. Numerous research efforts are dedicated to enhance speed, power efficiency, flexibility, and ease-of-use of these transceivers. This session includes some of the latest advances in this domain. The first transceiver paper employs a sub-sampling ring oscillator phase-locked loop (PLL) to obtain a large...
This paper discusses the applicability of CMOS (sub)-mm-Wave System-on-Chips in space explorations of the solar system, especially planetary missions. Specifically assessed are issues related to high levels of radiation encountered in deep space. To exemplify the type of technology infusion that is possible, we specifically feature the incorporation of a previously developed “self-healing” 12/48 GHz...
A power-scalable 2-Byte I/O operating at 12-Gb/s per lane is reported. The I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels. Measurements of a test chip fabricated in 32nm SOI CMOS technology demonstrate 1.4-pJ/b...
This paper presents some of the challenges unique to a multi-mode transceiver supporting LTE and LTE-Advanced. Implications of combining 2G, 3G and 4G in a single lineup are discussed. RF problems specific to 4G support are discussed and technical examples are given. Specific technical solutions are provided for duplex offset IIР2 in the receiver using calibration. Multiple transmit solutions are...
A clock-skew tolerant 8-bit 16x time-interleaved (TI) SAR ADC is presented that meets WiGig standard requirements with only background offset and gain calibrations. By using a “correct-by-construction”, timing-calibration-free global bottom-plate sampling scheme, the ADC achieves a sampling rate of 2.64GS/s while maintaining an ENOB of over 6 bits in the entire Nyquist band. The 40nm LP CMOS design...
The speed of Ethernet over copper cables has steadily increased by a factor of 10,000 over the last four decades, from 1Mb/s in the earliest Ethernet implementations to 10Gb/s in recent systems. This paper describes the design considerations on all levels of the 10GBASE-T design hierarchy that form the basis for the implementation of highly power-efficient AFEs in full-duplex 10GBASE-T transceivers...
Next-generation teleimmersive environments allow full-fledged collaboration of people in different geographical locations. The unique user experience poses new inter-sender synchronization requirement, which has not been investigated in past studies. The real-time nature of teleimmersive applications also introduce a tradeoff between synchronization quality and interactive quality during online synchronization...
This paper proposes replacing the analog phase interpolator in a phase-tracking ADC-based receiver with a digital data interpolator following the ADC. This allows for a blind ADC-based receiver that has a simpler adaptive DFE compared to previous implementations. Our measurements from a 65nm CMOS testchip confirm 7Gb/s operation for a 17dB channel loss.
In this paper, a 5.8 GHz DC-coupled CMOS radar sensor transceiver chip with a bandwidth of 1 GHz for human activity detection was designed and fabricated in IBM 180-nm process. This transceiver chip adopts the direct-conversion quadrature architecture. Variable gain amplifiers are used to provide different gains for the baseband signal in order to carry out different applications. A novel adaptive...
A wide locking range hybrid automatic gain control (AGC) loop for an ISM-band receiver is presented. It is composed of a three-stage Programmable Gain Amplifier (PGA), a differential-output Received Signal Strength Indicator (RSSI), a SAR ADC and control algorithm logic. The indicator's transfer function is realized in three segments, each of them covering 20dBm input range, in order to achieve higher...
This paper presents a reconfigurable current-commutating passive mixer for multi-standard applications. By having controllable transconductance and transimpedance stages, the gain, noise figure and linearity of the mixer can be reconfigured. Fabricated in 0.18 μm CMOS process, the mixer achieves a voltage-conversion-gain from 4 to 22 dB. The measured maximum IIP3 is 8.5 dBm and the minimum noise figure...
A high dynamic range, high detection sensitivity piecewise RSSI (received signal strength indicator) for software-defined radio (SDR) and cognitive radio (CR) receivers is proposed. With the reconfigurable limiting amplifiers, the RSSI achieves wide dynamic range and high detection sensitivity simultaneously. Two-path I/Q configuration RSSI structure is adopted to reduce the output voltage glitch...
This paper describes the implementation issues in designing a 1 tap current integrating half rate decision feedback equalizer. We introduce a new technique for designing an 8Gbps 1 tap half rate current integrating DFE in 40nm CMOS technology that draws 0.67mW from a 1.1V supply. The technique uses a delayed clock rather than speculation. This removes the speculation impact on power consumption and...
This paper reports on the world's first CMOS low noise amplifier (LNA) operating successfully on a radio telescope since October 15th, 2010. The radio telescope used in this work is the Synthesis Telescope operated by the Dominion Radio Astrophysical Observatory, NRC, and located near Penticton, BC, Canada. This paper describes the work that led to the installation of the LNA on the telescope and...
The paper presents the design and implementation of input/output interface circuits, fully compatible with low-voltage differential signal (LVDS) standard. Due to the low voltage differential transmission technique, the low power consumption and high transmission speed are achieved at the same time. The transmitter is implemented by a closed-loop control circuit and an internal bandgap voltage reference,...
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